The document describes a proposed novel 8T SRAM cell for ultra-low voltage applications. It begins with an objective to design an 8T SRAM cell that can operate at ultra-low voltages while maintaining low power consumption and improved write and read margins compared to a conventional 6T SRAM cell. It then analyzes the performance of the proposed 8T cell, finding it can operate reliably down to 335mV, with a hold static noise margin of 130mV. The 8T cell exhibits improved write and read stability compared to a 6T cell at ultra-low voltages. In conclusion, the 8T cell design meets the goals of enabling ultra-low voltage operation while improving performance.

1. DESIGN OF A NOVEL SINGLE-
ENDED, ROBUST 8T SRAM CELL
FOR ULTRA LOW-VOLTAGE,
APPLICATIONS
Presented By:
Rajesh Yadav
12ECP01P- M.Tech.(VLSI Design)
rajeshyadav@itmindia.edu
Thesis Phase - I
7th December 2013

2. Contents
• Objective
• Literature Survey
• Analysis of conventional 6T SRAM Cell
• Analysis of proposed 8T SRAM Cell
• References
2
rajeshyadav@itmindia.edu
Thesis Phase - I

3. • To overcome the bottleneck of 6T SRAM cell in
terms of low voltage operation.
• Design a single ended 8T SRAM cell with following
characteristics:
 Ultra Low Voltage operation
 Low power consumption
 Increased Write and Read Margin
3
Objective
rajeshyadav@itmindia.eduObjective Literature
Survey
6T SRAM Cell
Thesis Phase - I

4. • Most of the area of any SoC is consumed by memory.
• Minimum operating voltage of SRAM cell is 0.45V
reported till now as per my best Knowledge.
• Power dissipation will reduce, if we reduce its
operating voltage.
• As scale down the device (technology lower down)
leakage current is the major issue which causes great
power dissipation
4
Literature Survey
rajeshyadav@itmindia.eduObjective Literature
Survey
6T SRAM Cell
Thesis Phase - I

5. 5
Analysis of 6T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Thesis Phase - I

6. 6
Analysis of 6T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Operating Voltage = 1.8V
Thesis Phase - I

7. 7
Analysis of 6T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Operating Voltage = 0.45V
Thesis Phase - I

8. 8
Analysis of 6T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Operating Voltage = 0.40V
Thesis Phase - I

9. 9
Analysis of 6T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Operating Voltage = 0.40V
Thesis Phase - I

10. 10
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Thesis Phase - I

11. 11
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Response of Single ended 8T cell at operating Voltage = 900mV
Operation Hold Write 0 Write 1 read
WL 1 0 0 0
WWL/WBL 0/0 1/0 1/1 0/0
RWL/RBL 0/1 0/1 0/1 1/1
Thesis Phase - I

12. 12
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Response of Single ended 8T cell at operating Voltage = 340mV
Operation Hold Write 0 Write 1 read
WL 1 0 0 0
WWL/WBL 0/0 1/0 1/1 0/0
RWL/RBL 0/1 0/1 0/1 1/1
Thesis Phase - I

13. 13
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Response of Single ended 8T cell at operating Voltage = 335mV
Operation Hold Write 0 Write 1 read
WL 1 0 0 0
WWL/WBL 0/0 1/0 1/1 0/0
RWL/RBL 0/1 0/1 0/1 1/1
Thesis Phase - I

14. 14
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Response of Single ended 8T cell at operating Voltage = 335mV
Operation Hold Write 0 Write 1 read
WL 1 0 0 0
WWL/WBL 0/0 1/0 1/1 0/0
RWL/RBL 0/1 0/1 0/1 1/1
Thesis Phase - I

15. 15
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
Butterfly curve of proposed 8T SRAM Cell (Hold State) – HSNM =130mV
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
q(Volt)
qb (Volt)
HSNM of 8T SRAM
HSNM =130mV
Thesis Phase - I

16. 16
Analysis of Proposed 8T SRAM Cell
rajeshyadav@itmindia.eduLiterature survey
Current
Scenario
Requirements
ncurve of proposed 8T SRAM Cell
-1E-08
-5E-09
0
5E-09
1E-08
1.5E-08
2E-08
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
I(A)
q (Volt)
SVNM
WTI
WTV
Thesis Phase - I

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State Circuits, IEEE Journal vol. 41, Jan.2006, Issue 1 , pp.113-121
[2] M.F. Chang et al., A Differential Data Aware Power-supplied (D2AP) 8T SRAM Cell with Expanded Write / Read
Stabilities for Lower VDDmin Applications. Symposium on VLSI Circuits Digest of Technical Papers, pp. 156–157
(2009a)
[3] M. Yabuuchi et al., A 45 nm 0.6 V Cross-Point 8T SRAM with Negative Biased Read/Write Assist, Symposium on
VLSI Circuits Digest of Technical Papers, pp. 158–159 (2009) 30 2 SRAM Bit Cell Optimization
[4] L. Chang et al., An 8T-SRAM for variability tolerance and low-voltage operation in high performances caches. IEEE
J. Solid-State Circuits, 43, 4, April (2008)
[5] B.H. Calhoun et al., A 256 k Sub threshold SRAM Using 65 nm CMOS. Proceedings of IEEE International Solid-
State Circuits Conference (ISSCC), pp. 628–629, Feb 2006
[6] T.H. Kim et al., A High-Density Sub threshold SRAM with Data–Independent Bitline Leakage and Virtual Ground
Replica Scheme. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), pp. 330–331, Feb
2007
[7] I.J. Chang et al., A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential Read scheme in 90
nm CMOS. IEEE J. Solid-State Circuits 44(2), 650–658 (2009b)
[8] J. Wu et al., A Large rVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential
Technical Papers, pp. 101–102 (2010)
[9] T. Suzuki et al., 0.5 V, 150 MHz, Bulk-CMOS SRAM with Suspended Bit-Line Read Scheme, Proceedings of Sensing
and Fast Write-Back Scheme. Symposium on VLSI Circuits Digest of IEEE European Solid-State Circuits
Conference (ESSCIRC), pp. 354–357, Sept 2010
[10] V. Sharma et al., A 4.4 pJ/Access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier
redundancy. IEEE J. Solid-State Circuits, 46, 10 (2011a)
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17
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Expected
Outcomes References
Thesis Phase - I

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dynamic cell biasing, Symposium on VLSI Circuits Digest of Technical Papers, 2007, pp. 78–79.
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18
References
rajeshyadav@itmindia.eduTrade off
Expected
Outcomes References
Thesis Phase - I

19. Thank You For Your
Kind Attention
19Thesis Phase - I

20. Open For Discussion
20
???
Pre-Thesis Presentation , Phase - I