Comparision and evaluvation of 6T and 11T based SRAM.

1. Single Ended Schmitt Trigger
Based Robust Low Power
SRAM Cell
Guide : Prof. Joycee Mekie
Students: Ishant Anand
Vishwanath Hiremath

2. Introduction
• SRAM makes up a large portion of a system-on-chip area, and most
of the time, it also dominates the overall performance of a system.
• Mobile devices and emerging applications such as implanted
medical instruments and wireless body sensing networks,
necessitates the requirement of low-power SRAMs.
• Design of robust low power SRAM in deep sub-micrometer
technology, near/sub-threshold operation considering increased
device variations, reduced design margins and leakage power has
drawn great research attention.
• Different configurations of SRAM cells, such as 7T, 8T, 9T and 10T
cells, have been proposed over the time with a prime focus of
improvement in RSNM, HSNM and read-write conflicts.

3. 6T SRAM Cell

4. Write Operation in 6T SRAM Cell

5. Read Operation in 6T SRAM Cell

6. Schmitt Trigger (ST) Inverter

7. Proposed ST11T SRAM Cell Design

8. Proposed ST11T SRAM Cell Design
0 1

9. Proposed ST11T SRAM Cell Design
0 1
0
0
1
1
1 0

10. Proposed ST11T SRAM Cell Design
0 1
0
0
1
1
X
X
X
X
0

11. HOLD State
0 1
0
0
0
1
1
1
1
0
X
X
X
X
X

12. Write Operation
0 1
0
0
0
0
0
1
1
1
X
X

13. Write Operation
0 1
1
1
1
0
0
0
1
1
1
1

14. Write Operation
1
1
1
1
0
0
0
0
0
1
1 0

15. Write Operation
1
1
1
0
0
0
0
0
1
1 0
X
X
X

16. Write Operation
1
1
1
1
0
0
0
0
0
0
0
0

17. Write Operation
0
0
0
1
0
0
0
0
0
0
0 1

18. Write Operation
0
0
1
0
0
0
1
1
0
0
1

19. Read Operation
0 1
0
0
1
1
1
1
1
0
1 0

20. Read Operation
1 0
1
1
1
1
1
0
0
0
1
X

21. Cell Performance and Comparison
• Read stability: The proposed cell provides a 26% improvement in the mean
value of the RSNM as compared with the conventional 8T cell.
Comparison of RSNM of SRAM cells

22. • Write Ability: The write ability of an SRAM cell can be gauged in terms of
write margin. The proposed cell offers 1.85× and 1.20× higher write 0 and
write 1 margin, respectively, as compared with Chang 10T.
• Hold SNM: We observed that the ST-based cells have better HSNM as
compared with other cells due to improved characteristic of an ST inverter.
• Read Access Time(TRA): The TRA of ST11T Cell as compared with other
SRAM Cell which have similar read path are found to have almost the
same amount of TRA.
• Write Access Time(TWA): The ST11T Cell depicts very high TWA for
write 1, due to its single ended architecture as compared with ST1 and ST2
where writing is differential. Whereas, for ST11T shows lower TWA for
write 0 as compared with Chang 10T.

23. Critical Review
• The single-ended scheme reduces one half of the active power for BL
switching. However, it incurs penalty in terms of increased read-/write-
access time and degraded write 1 SNM at low supply voltages. This is the
major limitation of a single-ended SRAM structure.
• The working of the SRAM cell along with the simulation result, timing
diagram and comparison with the standard cells in terms of exhaustive list
of performance parameter has been presented well.
• The proposed bitcell employs read buffers to decouple storage nodes (Q
and QB) from BL to eliminate read-disturb problem along with the
requirement of asymmetric write assist mechanism for single-ended
writing. Therefore, there is no transistor sizing conflict for read and write
operations.
• The purposed SRAM cell has 2.02 times area overhead and 6.9 times high
ION/ IOFF ratio as compared to 6T SRAM cell. Nevertheless, due to its
high RSNM and significant immunity to half select disturb issue, the cell
could be an attractive choice for low Power applications.

24. Performance Parameter 6T 11T
Write 0 delay 54.319 ps 4.747 ps
Write 1 delay 64.989 ps 187 ps
Read 0 Access Time 50 ps 93.46 ps
Read 1 Access Time - 10.029 ps
Read Margin 92.11 mV 232.56 mV
Write Margin 385.5 mV 421.34 mV
Hold Margin 372.09 mV 376.2 mV
Performance Comparison Table

25. Hold Noise Margin(6T) Hold Noise Margin(11T)

26. Read Noise Margin(6T) Read Noise Margin(11T)

27. Write Noise Margin(6T) Write Noise Margin(11T)

28. Write 0 and Read 0 Access time with input low = 300mv

29. Write 1 and Read 1 Access time with input high = 700mv