3. SRAM Scaling Trends
ITRS Effective Cell
Reported Effective Cell
2
SRAM Cell Size (um )
2
SRAM Cell Size (um )
100
ITRS Single Cell
Reported Individual Cell
Reported Cell in Array
10
1
0.1
10
1
0.5x effective cell area
scaling difficult
0.1
700 600 500 400
300
200
100 80 70 60
10090
50
40
30
300
Technology N d ( )
T h l
Node (nm)
200
100 90 80 70
60
50
40
30
Technology N d ( )
T h l
Node (nm)
Individual SRAM cell area able to track ITRS guideline
Array area deviates from ITRS guideline at 90nm
Memory design no longer sits on the 0.5x area scaling trend!
5
On-Die L3 Cache siz (MB)
ze
Memory Scaling
Server processors
10
Itanium®
It i ®
Processors
Xeon®
Processors
1
180
160
140
120
100
80
60
Technology Node ( )
gy
(nm)
•
•
•
•
Memory latency demands larger last level cache (LLC)
Memory is more energy-efficient than logic
LLC approaches 50% chip area for desktop and mobile processors
LLC approaches 80% chip area for server processors
Vivek De, Intel 2006
6
3
4. 6-T SRAM Cell
• Improve CD control by unidirectional poly
• Relax critical layer patterning requirements
• Optimizing design rules is key
7
SRAM cell design trends
BL
BLB
IEDM 02
0.46x1.24μm
V
DD
’
GND
WL
Cell in 90nm
(1μm2)
•
•
•
•
•
Cell in 65nm
(0.57μm2)
Improve CD control by unidirectional poly
Relax critical layer patterning requirements
Optimizing design rules is key
Shorter bitline enables better cycle time and/or array efficiency
Full metal wordline with wider pitch achieves better RC
8
4
5. SRAM Cell Trends
0.242μm2 cell in 45nm from TSMC (IEDM’07)
0.346μm2 cell in 45nm from Intel (IEDM’07)
9
More SRAM Trends
0.15μm2 cell in 32nm from TSMC (IEDM’07)
10
5
6. Ion/Ioff: Cell Read and Leakage
H. Pilo, IEDM 200611
SRAM Cell/Array
Hold stability
WL
VDD
Read stability
M2
Write stability
M5
Read current (access time)
Access Transistor
Pull down
M1
BL
Pull up
Q
M4
Q
M6
M3
BL
12
6
7. SRAM Design – Hold (Retention) Stability
Load
WL
VDD
PL
AXL
PR
‘1’
‘0’
AXR
Access
NL
NR
NPD
BL
BL
Data Retention
Leakage
Scaling trend:
Increased gate leakage + degraded ION/IOFF ratio
Lower VDD during standby
PMOS load devices must compensate for leakage
13
SRAM Cell Mismatch
ΔVTh ∝
K. Zhang, Intel
1
Cox WL
Due to RDF
14
7
8. The Data-Retention Voltage (DRV) of SRAM
VDD
0
M5
V1
Leakage
current
M2
M4
DRV Condition:
0
M3
V2
M6
VDD
Leakage
current
∂V1
∂V2
=
Left inverter
∂V1
∂V2
When Vdd scales down to DRV, the
voltage transfer curves (VTC) of the
internal inverters degrade to such a
level that retention static noise margin
(SNM) of the SRAM cell reduces to
zero.
, when VDD = DRV
Right inverter
VTC of SRAM cell inverters
0.4
VDD=0.4V
2
0.3
0.2 V =0.18V
DD
0.1
VTC1
VTC2
0
Qin, ISQED’04
0
0.1
0.2
V1 (V)
0.3
0.4
15
Monte-Carlo Simulation of DRV Distribution
300
250
Histogram of cell #
VDD
M1
200
150
100
50
0
0
50
100
150
200
250
Simulated DRV of 1500 SRAM cells (mV)
300
16
8
9. H. Pilo, IEDM 200617
Read Stability – Static Noise Margin (SNM)
VDD
1
PR
VL
VR
Read SNM[1]
AXR
VR (V)
NR
0.5
90nm simulation
0
0
0.5
1
VL (V)
• Read SNM is typically the most stringent constraint
[1] E. Seevinck, JSSC 1987
18
9
10. SRAM Design – Read Stability
Load
WL
VDD
PL
AXL
PR
AXR
‘1’
V>0
Access NL
NR
NPD
BL
Retention fluctuations
BL
Read margin and
retention margin
[Bhavnagarwala, IEDM’05]
19
Read Stability – N-Curve
•
A, B, and C correspond to the two
stable points A and C and the metap
stable point B of the SNM curve
•
When points A and B coincide, the
cell is at the edge of stability and a
destructive read can easily occur
20
10
11. H. Pilo, IEDM 200621
Write Stability – Write Noise Margin (WNM)
VDD
1
90nm simulation
PR
VL
VR
AXR
VR (V)
NR
0.5
WNM[1]
0
0
0.5
1
VL (V)
• Write stability is becoming more stringent with scaling
• Optimizing read and write stability at the same time is difficult
[1] A. Bhavnagarwala, IEDM 2005
22
11
12. Write Stability – BL/WL Write Margins
1.2
1.2
1
0.8
0.6
Voltage (V)
(
V o ltag e (V )
1
BL
0.4
0.2
WM
0
0.00E+00
-0.2
2.00E-08
0.8
0.6
0.4
WM
WL
0.2
0
4.00E-08
6.00E-08
Time (s)
8.00E-08
1.00E-07
0.00E+00
-0.2
2.00E-08
4.00E-08
6.00E-08
8.00E-08
1.00E-07
Time (s)
Highest BL voltage under which write is possible when BLC is kept
precharged (left)
Difference between VDD and lowest WL voltage under which write is
possible when both bit-lines are kept precharged (right)
Can be directly measured in large memory arrays via BL currents
23
Write Stability – Write Current (N-Curve)
[1] C. Wann et al, IEEE VLSI-TSA 2005
24
12
13. H. Pilo, IEDM 200625
SRAM Design – Read/Write Stability
Load
WL
Cell Stability
VDD
PL
AXL
Cell Trip
Voltage
PR
AXR
‘1’
V>0
Access NL
Read U
R d Upset
t
Occurs
Cell Read
Voltage
NR
NPD
BL
BL
Technology Scaling
H. Pilo, ISSCC’2005
Read margin is typically the most stringent constraint
Cell read voltage must stay below cell trip voltage
Harder to achieve with process induced variations
Noise margin degraded with technology scaling
26
13
14. 6-T SRAM Static/Dynamic Stability
Read Margin
SNM: pessimistic
Write Margin
WNM: optimistic
[1] E. Seevinck, JSSC 1987; [2] A. Bhavnagarwala, IEDM 2005
27
H. Pilo, IEDM 200628
14
