Project Report Of SRAM Design

AVLSI Project#1: SRAM Design and
Layout
EECT 7325
Summer 2014
Guided By:
Prof. Carl Sechen (Professor-Electrical Engineering)
Mr. Akshay Sridharan (Teaching Assistant)
Created By:
Aalay Kapadia
Net ID: adk130330
Tao Pu
Net ID: txp131030

EE7325 PROJECT #1 Page 1 of 21
Author: Aalay Kapadia & Tao Pu
1. Introduction
In the project#1, IBM 130nm process is used to design and manual layout a 128
word SRAM, with word size 10bits. Cadence's Virtuoso is applied for layout
editing, DRC and LVS running and circuit simulation.
2. SRAM Architecture
The SRAM includes the several parts: 6T Memory cell, Column decoder, Row
decoder, Sense amplifier, Write enable, Clock inverter.
2.1 SRAM Memory Cell
SRAM memory cell is the basic block of SRAM, the size of memory cell accounts
for most of array size. 6T SRAM cell is applied in this project. 6T cell uses 2 back-
to-back inverters to latch the data being written in by Bit Line (BL) or Bit Line Bar
(BL-). While reading, BL is pre-charged to high. The schematic view and layout of
6T memory cell is shown in Figure 1, 2:
Figure 1 6T Cell Schematic

Figure 2 6T cell layout
The size of 6T cell layout is 2.42 2.83

2.2 SRAM Memory Cell Noise margin measurements

Figure 3 6T cell noise margin
We can see that the noise margin of 6T cell is 0.45v from Figure 3
2.3 Array Architecture
The size of a memory cell is 2.42 2.83 . The total number of memory
cells is determined by the size of the SRAM, which are 128 words in this project.
Total size of SRAM = 128 10=
The scheme of SRAM array is mainly calculated by the aspect ratio (AR) to
determined value and round the result to integer. In this project, we want to get an
optimal AR of 1, and assume words are stored in per row.
So, words are stored per row, while bits for row decoder. Hence, array
architecture is 32 40.
2.4 Column Decoders
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Noise Margin
NM=0.45V

The total number of bits available for column decoding is 2 and technique applied
in this project is conventional column decoder. Factors such as delay, practical
implementation and path effort are taken into account while designing the
architecture of column decoder. 2 Stages are inserted between NAND2 and
inverter to achieve better performance, rendering a total of 4 stages for generating
A which connecting to NMOS of T-gate, and 3 stages for generating ̅ which
connects to PMOS of T-gate.
These values are chosen after deliberate calculation:
Figure 4 Column Decoder Symbols
Then , ,
So
We chose number of stage =5, then ̂ √

Figure 5 Column Decoder with T-gate Schematic

Figure 6 Column Decoder with T-gate Layout
2.5 Row Decoders
The total number of bits available for row decoding is 5. Same to the calculation of
column decoder, factors such as delay, implementation and path effort are taken
into account while designing the architecture of row decoder.
Figure 7 Row Decoder Symbols
Then , ,
So

Figure 8 Row Decoder Schematic View
Figure 7 Row Decoder Layout

2.6 Sense amplifier
We use the current mode sense amplifier to amplify the output signal. To get the
appropriate size of the sense amplifier, all the NMOS' sizes are fixed at 280nm,
and sweep the sizes of PMOS. After being tested, the appropriate size for PMOS is
2.8
To the output buffer, two minimum sized neutral skewed inverters were chose
(including NMOS: 280nm, PMOS: 840nm).
Figure 9 Sense Amplifier Schematic

Figure 10 Sense Amplifier Layout
2.7 Write Enable
Two sets of write enable respectively connect with BL and BL. Each write enable
consists of one tri-state inverter to select enable signal. Three stages are designed,
2 of which are inverter which are applied to speed up the pass of enable signal and
another one is T-gate. The calculation of the inverters’ size is shown below:
Then , ,
So

Figure 11: Write Enable-Schematic View
Figure 12 Write Enable Layout

2.8 Clock Inverter
Clock signal is added to manipulate pre-charge and buffers are added to minimize
the delay.
Then , ,
So
Figure 13 Clock inv Schematic

Figure 14 Clock inv Layout
3. Summery
3.1 Final Layout and Schematic
The size of the final SRAM with all peripherals is 126.4 152.57 , and the
total area is 19284.848 .
The size of the final SRAM is 81.87 96.81 , and the total area is
7925.8347 .

Figure 15 Final SRAM Layout
Figure 16 Final SRAM with peripherals Layout

Figure 17: Final SRAM with peripherals Schematic
3. 2 DRC and LVS Report
Figure 18 Final SRAM layout has passed DRC

Figure 19 Final SRAM layout has passed LVS
3.3 Waveforms and Performance
To measure the worst case, we choose row address as vector 0 0 0 0 0, and column
address as 1 1, which means the cell located in the 1st row and 8th column is being
investigated. The waveform in figure clearly shows SRAM's write and read
functions properly.
The worst case delay for reading a 0 is, as shown in figure, 369ps. The worst case
delay for writing is found out by Keep narrowing the difference between the rise
edge of write data and the fall edge of write enable until SRAM cannot read out
proper data.

Figure 20 the delay of reading a 0 is 369ps
SRAM successfully reads out the 1, which means the 1 was successfully written in
to memory cell. The delay for reading a 1, therefore, is around 387ps.

Figure 21 SRAM can read out the 1
The same procedure is applied in finding the delay of writing a 1. The delay for
writing a 1 is also approximately 300ps.
Figure 22 SRAM successfully writes in and reads out the 1

The same procedure is applied in finding the delay of writing a 0. The delay for
writing a 0 is also approximately 307ps.
Figure 23 SRAM successfully writes in and reads out the 0

Project Report Of SRAM Design

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Project Report Of SRAM Design