The document discusses floorplanning in integrated circuit design. Floorplanning involves tentatively placing functional blocks on a chip to optimize the design for area, wirelength, delay and other factors like noise and heat dissipation. It describes the goals and inputs/outputs of floorplanning. Floorplanning styles can be slicing, non-slicing, full custom, standard cell or gate array. Algorithms used for floorplanning include Stockmeyer, simulated annealing, linear programming and sequence-pair based approaches. Floorplans can be represented by normalized polish expressions.

1. Floorplanning
DoVLSI Presentation

2. RTL Design Flow

3. Physical Design –Overall Flow

4. Floorplanning
• Floorplan of an integrated circuit
is a schematic representation of
tentative placement of its major
functional blocks.
• Depending on the design
methodology being followed, the
actual definition of a floorplan
may differ.

5. Why Floorplanning?
The floorplanning problem is to plan the
positions and shapes of the modules at the
beginning of the design cycle to optimize the
circuit performance:
– chip area
– total wirelength
– delay of critical path
– routability
– others, e.g., noise, heat dissipation, etc.

6. Floorplanning
Goals
• Assign shape and location of blocks.
• Decide location of I/O pads.
• Decide location and number of power pads.
• Decide type of power distribution.
• Decide location and type of clock distribution.
Objectives
• Keep highly connected blocks physically close to each other.
• Minimize chip area.
• Minimize delay.

7. 7
Floorplanning
Input
Set of blocks.
Area estimation.
Possible block shapes.
Number of terminals.
Netlist.
Output
Shapes (Area & Aspect Ratio) and
locations of blocks.
Soft Blocks
• Flexible shape
• I/O positions not yet determined
Hard Blocks
•Fixed shape
•Fixed I/O pin positions

8. Design Styles
Full Custom
• Floorplanning is needed.
Standard Cell
• Fixed cell dimensions. Floorplanning translates into a
placement problem.
• Floorplanning may be required for large cells if they are
partitioned into several blocks.
Gate Array
• Placement problem.

9. Slicing and Non-Slicing Floorplan
Slicing Floorplan:
One that can be
obtained by repetitively
subdividing (slicing)
rectangles horizontally or
vertically.
Non-Slicing Floorplan:
One that may not be
obtained by repetitively
subdividing alone.

10. `
10
Floorplanning
Area
Deadspace
Minimizing area = Minimizing deadspace
Wire length estimation
• Exact wire length not known until after routing.
• Pin position not known.
• How to estimate?
• Center to center estimation.

11. Floorplanning Algorithm
• Stockmeyer algorithm
• Simulated annealing
• Linear programming
• Sequence-pair based floorplanning

12. 12
Floorplanning
• Represent floorplan by normalized polish expression.
7 5
6
1
4
2
3
E = 16H7H25HV34HV

13. Encounter Floorplan