This document analyzes the static noise margin and power dissipation of a proposed low voltage swing 8T SRAM cell. It presents the proposed SRAM cell, its operation, and compares its static noise margin and power dissipation to conventional 6T and 11T SRAM cells under varying conditions of cell ratio, pull-up ratio, temperature, supply voltage, and bit line capacitance. The analysis shows that the proposed 8T SRAM cell has better read and write stability and reduced power dissipation due to its lower voltage swing compared to conventional SRAM cells. Future work could focus on improving its hold stability and reducing leakage.

1. ANALYSIS OF STATIC NOISE MARGIN
AND POWER DISSIPATION OF A
PROPOSED LOW VOLTAGE SWING 8T
SRAM CELL
Presented by:
Santosh Kumar Chhotray
Student (M.Tech )
National Institute of Technology, Durgapur
Dept of ECE

2. CONTENTS
 Introduction
 Parameters of SRAM
 Proposed SRAM cell
 Proposed SRAM cell operation
 Dynamic power
 Static Noise Margin
 Result and Discussion
 Future Scope
 References
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3. INTRODUCTION
 Purpose of memory
 SRAM
 6T SRAM
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4. PARAMETERS OF SRAM
 Hold Stability
 Read Stability
 Write Stability
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5. PROPOSED SRAM CELL
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6. WRITE OPERATION
WRITE ‘0’
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7. WRITE ‘1’
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8. READ STATIC NOISE MARGIN
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Cell Ratio SNM Proposed
8T SRAM(mV)
SNM 11T
SRAM(mV)
SNM 6T
SRAM(mV)
0.6 289 271 100
0.8 298.5 280 102.5
1.0 311.8 291 104.6
1.2 336.6 299 107
1.4 349.2 308 108
1.6 370.4 319 112
1.8 391.8 334 116.7
2.0 403.1 340 123

9. CONTI..
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10. WRITE STATIC NOISE MARGIN
Pull up Ratio Write SNM
Proposed 8T
SRAM (mV)
Write SNM 11T
SRAM (mV)
Write SNM 6T
SRAM (mV)
1.05 252.3 241 92.9
1.2 253.6 242 94
1.4 259.1 244 94.6
1.6 263.4 246 95
1.8 268 249 95.5
2.0 272.5 250 96
2.1 274 251 96.7
2.2 279.8 253 97.8
2.4 286.3 257 99.2
2.6 290 259 100.4
2.8 295.4 260 102.3
3.0 301.6 262 104
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11. CONTI..
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12. DYNAMIC POWER
 Dynamic power of SRAM
where = Load capacitance, = Activity factor,
=Clock frequency, = Voltage swing at
output node.
dynamic dd SwingP CV V fα=
C α
f SwingV
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13. CONTI..
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14. VARIATION OF POWER DISSIPATION
WITH TEMP.
Temperature (0
C) Proposed 8T
SRAM Power
dissipation (pW)
11T SRAM Power
dissipation (pW)
6T SRAM Power
dissipation (pW)
0 26.1732 39.5402 66.5688
5 27.0819 40.2024 66.4591
10 27.9182 41.0517 67.9243
15 28.6613 42.1322 68.0234
20 29.8731 43.5032 68.8615
25 31.0177 45.3026 69.7287
27 31.7611 46.1243 70.5036
30 32.1181 47.5201 72.9018
35 35.5132 50.3854 76.0813
40 38.7367 54.1782 80.9964
45 41.8153 59.3794 84.2878
50 43.1241 66.8385 89.2718
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15. CONTI..
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16. VARIATION OF POWER DISSIPATION
WITH SUPPLY VOLTAGE
Supply Voltage
(Volts)
Proposed 8T
SRAM Power
dissipation (pW)
11T SRAM
Power
dissipation (pW)
6T SRAM Power
dissipation (pW)
5.0 59.1687 68.4357 396.5366
4.5 55.8921 64.7294 340.8164
4.0 49.5612 59.6143 274.1283
3.5 44.1181 55.6481 196.2356
3.0 38.8792 50.0972 129.9901
2.5 33.0132 46.1243 70.5036
2.0 28.6911 42.6591 67.3492
1.5 23.0982 37.2356 59.5460
1.0 20.2561 32.8437 51.4837
0.5 16.7115 26.3189 46.8218
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17. CONTI..
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18. VARIATION OF POWER DISSIPATION
WITH BIT LINE CAPACITANCE
Capacitance (pF) Proposed 8T
SRAM Power
dissipation (pW)
11T SRAM
Power
dissipation (pW)
6T SRAM Power
dissipation (pW)
5.0 198.67 209.4 267.9
4.0 151.01 167.9 240.19
3.0 101.98 125.2 213.32
2.0 89.11 103.7 198.82
1.5 70.57 85.1 174.24
1.0 54.80 69.3 139.42
0.8 49.23 61.5 118.45
0.5 42.39 55.08 99.67
0.1 32.88 46.2 70.5
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19. CONTI..
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20. CONCLUSION
 Better read and write stability
 Reduced voltage swing results in reduced
dynamic power dissipation
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21. FUTURE SCOPE
 Hold stability
 Effective reduction of leakage in SRAM
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22. REFERENCES
 Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene, “Read Stability
and Write-Ability Analysis of SRAM Cells for Nanometer Technologies”, IEEE
Journal of Solid-State Circuits, Vol. 41, no.11, pp. 2577-88, Nov. 2006.
 C. Wann, “SRAM cell design for stability methodology”, IEEE VLSI-TSA,
pp. 21-22, Aug 2004.
 N. Gierczynski, B. Borot , N. Planes, H. Brut, “A new combined methodology
for write margin extraction of advanced SRAM”, IEEE Int. Conf. On
Microelectronic Test Structures, pp.97-100, 2007.
 R. K. Singh, Shilpi Birla, Manisha Pattanaik, “Characterization of 9T SRAM
Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia
Applications”, IACSIT International Journal of Engineering and Technology,
Vol. 3, no. 6, pp. 696-700, December 2011.
 S. Singh Tomar, Madhav Singh, Shyam Akashe, “Static Noise Margin Analysis
during Read Operation of 7T SRAM Cells in 45nm Technology for Increase Cell
Stability”, International Journal of Engineering Science and Technology
(IJEST), Vol. 3, no. 9, pp. 7180-86, September 2011.
 D. Mukherjee, H. K. Mondal and B.V.R. Reddy,” Static Noise Margin Analysis
of SRAM Cell for High Speed Application”, IJCSI International Journal of
Computer Science Issues, Vol. 7, no. 5, pp. 2160-71 September 2010.
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23. CONTI..
 Vikas Nehra, Rajesh Singh, Neeraj Kr. Shukla, Shilpi Birla, Mahima Kumar,
Ankit Goel, “Simulation & Analysis of 8T SRAM Cell’s Stability at Deep Sub-
Micron CMOS Technology for Multimedia Applications”, Canadian Journal on
Electrical and Electronics Engineering Vol. 3, no. 1, pp-11-16, January 2012
 Neil H. E. Weste, David Harris, Ayan Banerjee, "CMOS VLSI Design", Pearson
Education, 3rd Edition, pp. 55-57.
 A. Bhavnagarwala, “Fluctuation limits & scaling opportunities for CMOS
SRAM cells”, IEDM, pp.659-662, 2005.
 K. Zhang et al. “A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with
integrated column-based dynamic power supply”, IEEE J. Solid-State Circuits,
Vol.41, no.1, pp.146-51, Jan. 2006.
 K. Takeda, “Redefinition of write-margin for nextgeneration SRAM and write-
margin monitoring circuit”, ISSCC, pp.2602-2603, 2006.
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24. THANK YOU
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