Floorplanning involves the arrangement of logical blocks on a silicon chip through a series of steps, including partitioning designs, defining core dimensions, and placing pre-placed cells. Key components of this process include power planning, which ensures proper connections to power sources using a grid structure for multiple supply points, and the encapsulation of pre-placed cells with decoupling capacitors. The overall goal is to optimize the layout for efficient functioning of the integrated circuit.

1. Floorplanning is basically the arrangement of logical blocks (i.e. multiplexer,
AND, OR gates, buffers) on silicon chip.

2. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Partition and synthesize larger designs into smaller modules
consisting of IP’s and std cells

3. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Define width and Height of ‘core’ and ‘Die’ using the physical area of
synthesized netlist, utilization factor and aspect ratio

4. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Define locations of pre-placed cells

5. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Place de-coupling capacitors surrounding pre-placed cells

6. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• Power Planning

7. Floorplanning is basically the arrangement of logical blocks (i.e.
multiplexer, AND, OR gates, buffers) on silicon chip.
It is attained by following steps:
• IO Pin/Pad placement

8. • We have defined the Width and Height of the core.
• Also defined the locations of pre-placed cells.
• We have encapsulated the Pre-placed Cells by Decoupling capacitor.
• We will do the Power Planning for the Chip

9. Power Planning
Power Planning is to connect each cell in the design to the power source i.e. VDD and VSS.
• If observed, while drawing any circuit on
paper, we have only one 'vdd' at the top
and one 'vss' at the bottom.
• But on a chip, it becomes necessary to
have a grid structure for power source,
with more than one 'vdd' and 'vss‘.
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10. We will convert the power lines into the Power Mesh.

11. DECAP1
D
Block a Block b
4
Pre-placed
DECAP2
Cells
Block c
DECAP3
Die
Core

12. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Core

13. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd

14. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd

15. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd

16. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd

17. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd
Contact

18. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd
Contact

19. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd
Contact

20. The Power mesh will look as below.

21. Vss
Vdd
Contact

22. DECAP1
D
Block a Block b
4
DECAP2
Block c
DECAP3
Die
Vss Core
Vdd
Contact