A basic presentation on Layout Extraction

1. LAYOUT EXTRACTION

2. AGENDA
• Digital Design Flow
• Basics of Layout
• About Layout Extractor
• Tools used
• Steps to Extract layout
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3. Digital Design Flow
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Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Verilog/
VHDL
Library
Std., Cell.
Library
Look up
Table for
timing
Tech file
For layout
values
Tech file
For RC
Parasite
extraction

4. Basics of Layout
• Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
– Must follow a technology rule
• Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
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5. What Are Layout Extractors??
• Once the layout is made, there always is parasitic
capacitances and resistances associated with the
design.
• This is because of the compact layouts to make the
chips smaller. More you make compact layout more
will it introduce these parasitic components.
• These interferes in the functioning and performance of
the circuit in terms of timing, speed and power
consumption.
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6. Contd…
• Examine the inter-relationship of mask layers
to infer the existence of transistors and other
components
• Related to Design Rule Checkers
– Design-rule Verification
• Some form of layout extraction is usually done
to create data for back annotation
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7. Tools used for Extraction
• FastCap, FastHenry
• Star-RCXT
• QRC
• Calibre xACT3D
etc…
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8. Steps to Extract a Layout
• Create Layout Cellview
• Design Rule Checking
• Layout Parameter Extraction
• Layout vs. Schematic Comparison
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Courtesy:http://www.egr.msu.edu/classes/ece410/mason/files/TutorialB.pdf
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9. Step1: Create Layout Cellview
From the schematic, we can draw the layout cellview
From the Library Manager window, Select File => New => Cellview
(Virtuoso is the main layout editor of Cadence design tools)
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10. Step2:Design Rule Checking
• After you have finished your layout, an automatic program will check
each and every polygon in your design against these design rules
and report violations. This process is called Design Rule Checking
(DRC) and MUST be done for every layout to ensure it will function
properly when fabricated.
• After the DRC is complete, the bottom line in the CIW(Command
Interpreter Window) will show “# Total errors found”
• The DRC will be successful when you see the results saying “0 Total
errors found”
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11. Step3: Layout Parameter
Extraction
• mask layout contains only physical data
• Extraction process identifies the devices from the layout and
generates a SPICE-like netlist and other files necessary to complete
the design process
• In the Virtuoso Layout Editing window select Verify => Extract
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12. Extracted Layout
Before After
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13. Conclusion
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Data Preparation
Draw Schematic
(Virtuoso)
Logic Simulation
(Verilog-XL)
Pre-layout Simulation
(Spectre)
Layout
(Virtuoso)
Design Rule Check
(Calibre)
Layout Versus
Schematic Check
(Calibre)
Extraction
(Calibre)
Post layout simulation
(HSPICE)

14. THANK YOU
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