This document proposes a new SRAM bitcell design based on Schmitt triggers (STs) for improved read stability and write ability at ultra-low voltages. ST-based SRAM bitcells address the conflicting requirements of read and write operations in a conventional 6T bitcell. The ST operation provides better read stability and write ability compared to a standard 6T bitcell. The document describes previous SRAM research, the need for ST-based designs, performance analysis of different bitcell architectures including 6T, 8T, 9T and 10T cells, and concludes the ST cell has the best performance in terms of leakage power reduction and energy efficiency.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Ieee Xpert
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
An Innovative Design solution for minimizing Power Dissipation in SRAM CellIJERA Editor
Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell Ieee Xpert
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
A Single-Ended With Dynamic Feedback Control
8T Subthreshold SRAM Cell
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
An Innovative Design solution for minimizing Power Dissipation in SRAM CellIJERA Editor
Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
Performance of Fractional-Slot Winding PM Machines due to Un-even Coil Turns ...IJPEDS-IAES
PM machines in which slot number and pole number combination differs by
one have to be configured with asymmetric winding pattern in order to
maximize it back-emf performance. However, this asymmetric winding
configuration inherently results an unwanted Unabalanced Magnetic Force
(UMF). Investigations of electromagnetic performance of fractional-slot
asymmetric winding PM machines using 2-D Finite-Element Analysis are
presented. The investigations are mainly driven by the effort of minimizing
the UMF. By employing techniques such as non-uniform number of coil
turns in every tooth and asymmetric design of stator tooth, the UMF are
expected can be minimized. The investigations show that the radial
component of UMF has greater effect than the tangential component on the
UMF itself. In all proposed techniques, a slight reduction of machine torque
performance is inevitable.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STUDY OF SPIN TRANSFER TORQUE (STT) AND SPIN ORBIT TORQUE (SOT) MAGNETIC TUNN...elelijjournal
Magnetic Random Access Memory (MRAM) is a promising candidate to be the universal non-volatile (NV) storage device. The Magnetic Tunnel Junction (MTJ) is the cornerstone of the NV-MRAM technology. 2- terminal MTJ based on Spin Transfer Torque (STT) switching is considered as a hot topic for academic and industrial researchers. Moreover, the 3-terminal Spin Orbit Torque (SOT) MTJ has recently been considered as a hopeful device which provides an increased reliability thanks to independent write and read paths. Since both MTJ devices (STT and SOT) seem to revolutionize the data storage market, it is necessary to explore their compatibility with very advanced CMOS processes in terms of transistor sizing and performance. Assuming a good maturity of the magnetic processes that would enable to fabricate small junctions, simulation results show that the existing advanced sub-micronic CMOS processes can drive the required writing current with reasonable size of transistors confirming the high density feature of MRAMs. At 28 nm node, the minimum transistor size can be used by the STT device. The SOT device shows remarkable energy efficiency with 6× improvement compared with the STT technology. Results are very encouraging for future complex hybrid magnetic/CMOS integrated circuits (ICs).
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
Performance of Fractional-Slot Winding PM Machines due to Un-even Coil Turns ...IJPEDS-IAES
PM machines in which slot number and pole number combination differs by
one have to be configured with asymmetric winding pattern in order to
maximize it back-emf performance. However, this asymmetric winding
configuration inherently results an unwanted Unabalanced Magnetic Force
(UMF). Investigations of electromagnetic performance of fractional-slot
asymmetric winding PM machines using 2-D Finite-Element Analysis are
presented. The investigations are mainly driven by the effort of minimizing
the UMF. By employing techniques such as non-uniform number of coil
turns in every tooth and asymmetric design of stator tooth, the UMF are
expected can be minimized. The investigations show that the radial
component of UMF has greater effect than the tangential component on the
UMF itself. In all proposed techniques, a slight reduction of machine torque
performance is inevitable.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
Static-Noise-Margin Analysis of Modified 6T SRAM Cell during Read Operationidescitation
As modern technology is spreading fast, it is very
important to design low power, high performance, fast
responding SRAM(Static Random Access Memory) since they
are critical component in high performance processors. In
this paper we discuss about the noise effect of different SRAM
circuits during read operation which hinders the stability of
the SRAM cell. This paper also represents a modified 6T
SRAM cell which increases the cell stability without
increasing transistor count.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a
6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and
operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET
back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power
technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with
optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design
parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal
decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a
6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and
operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET
back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power
technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with
optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design
parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal
decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV
and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells
with minimal impact on the subthreshold leakage currents, performance and energy consumption.
This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this
investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing
the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.
Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.
A Comparitive Analysis of Improved 6t Sram Cell With Different Sram CellIJERA Editor
High speed and low power consumption have been the primary issue to design Static Random Access Memory (SRAM), but we are facing new challenges with the scaling of technology. The stability and speed of SRAM are important issues to improve efficiency and performance of the system. Stability of the SRAM depends on the static noise margin (SNM) so the noise margin is also important parameter for the design of memory because the higher noise margin confirms the high speed of the SRAM cell. In this paper, the improved 6T SRAM cell shows maximum reduction in power consumption of 88%, maximum reduction in delay of 64% and maximum SNM of 17% increases compared with 7T SRAM cell.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
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Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based on ST for Better Read Stability and Write Ability
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 6, Issue 4(May. - Jun. 2013), PP 56-61
www.iosrjournals.org
www.iosrjournals.org 56 | Page
Implementation of an Efficient SRAM for Ultra-Low Voltage
Application Based on ST for Better Read Stability and Write
Ability
C.Ramya Shruthi (1)
,S.Rambabu (2)
Department Of ECE, S.R.E.C, Nandyal
Assistant Professor, S.R.E.C, Nandyal.
Abstract: Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold
voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We
analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for
ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design
requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-
stability as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to
propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and
less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were
done using DSCH and Microwind.
Index Terms: read stability, write ability, Schmitt trigger.
I. Introduction
PORTABLE electronic devices have extremely low power requirement to maximize the battery
lifetime. Various device-/circuit-architectural-level techniques have been implemented to minimize the power
consumption. Supply voltage scaling has significant impact on the overall power dissipation.With the supply
voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly (to the
first order). However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations
increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing
Minimum-sizedtransistor. These minimum geometry transistors are vulnerable to interdie as well as intradie
process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness
(LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell,
resulting in asymmetrical characteristics. The combined effect of the lower supply voltage along with the
increased process variations may lead to and increased memory failures such as read-failure, hold-failure, write-
failure, access-time failure. Moreover, it is predicted that embedded cache memories, which are expected to
occupy a significant portion of the total die area, will be more prone to failures with scaling.
Figure 1. Demonstration of ultra low power SRAM significance from three state-of-the-art examples targeting
energy constrained applications.
II. Previous Sram Bitcell Research
Several SRAM bitcells have been proposed having different design goals such as bit density, bitcell
area, low voltage operation and architectural timing specifications. In the four transistor (4T) loadless bitcell,
pMOS devices act as access transistors. The design requirement is such that pMOS OFFstate current should be
more than the pull-down
nMOS transistor leakage current for maintaining data “1” reliably. With increasing process variations
and exponential dependence of the subthreshold current on the threshold voltage, satisfying this design
equirement across different process, voltage, and temperature (PVT) conditions may be challenging. 5T bitcell
2. Implementation Of An Efficient SRAM For Ultra-Low Voltage Application Based On ST For Better
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consists of asymmetric cross coupled inverters with a single bitlin. Separate bitline precharge voltages are used
for read and write operations. The intermediate read bitline precharge voltage requires a dc–dc converter.
Tracking the read precharge voltage across PVT corners would require additional design margins in bitcell
sizing and may limit its ap-plicability. A 6T bitcell comprises of two cross-coupled CMOSinverters, the
contents of which can be ac cessed by two nMOS access transistors. The 6T bitcell is the “de facto” memory
bitcell used in the present SRAM designs. A single-ended 6T bitcell uses a full transmission gate at one side.
Write-ability is achieved by modulating the virtual-VCC and virtual-VSS of one of the inverters. The
single-ended 7T bitcell proposed separately by Tawfik et al. and Suzuki consists of single-ended write operation
and a separate read port. Single-ended write operation in this 7T bitcell needs either asymmetrical inverter
characteristics or differential VSS/VCC bias. Takeda et al. have proposed another single-ended 7T bitcell in
which an extra transistor is added in the pull-down path of one of the inverters. During read mode, the extra
transistor is turned OFF, isolating the corresponding storage node from VSS. This results in read-disturb-free
operation. In a differential 7T bitcell, the feedback between the two inverters is cut off during the write
operation. Successful write operation necessitates skewed inverter sizing, resulting in asymmetrical noise
margins. In a single-ended 8T bitcell, extra transistors are added to the conventional 6T bitcell to separate read
and write operation. Liu and Kursun have proposed a 9T
Fig2:circuit diagram of some of sram structures.
III. Need Of Schmitt Trigger Based Sram Designs
In order to resolve the conflicting read versus write design requirements in the conventional 6T bitcell,
the Schmitt Trigger (ST) principle for the cross-coupled inverter pair is applied. A Schmitt trigger is used to
modulate the switching threshold of an inverter depending on the direction of the input transition. In the existing
ST SRAM bitcells, the feedback mechanism is used only in the pull-down path, as shown in figure1.During
input transition, the feedback transistor (NF) tries to preserve the logic “1” at output node by raising the source
voltage of pull-down nMOS (N1). This results in higher switching threshold of the inverter with very sharp
transfer characteristics. Since a read-failure is initiated by a input transition for the inverter storing logic “1,”
higher switching threshold with sharp transfer characteristics of the Schmitt trigger gives robust read operation.
For the input transition, the feedback mechanism is not present. This results in smooth transfer
characteristics that are essential for easy write operation. Thus, input-dependent transfer characteristics of the
Schmitt trigger improves both read-stability as well as write-ability of the SRAM bitcell. To maintain the clarity
of the discussion, the ST bitcell in [10][11] is termed the “ST-1” bitcell while the other ST bitcell is termed the
“ST-2” bitcell shown in the Figures3 and 4 respectively.
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Fig3:st-1 cell
Fig4:layout of st-1 cell
Fig4:st-2 cell
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Fig5:st-2 layout diagram
IV. Performance Analysis Of Sram Architectural Co-Design
This section resents the performance analysis of SRAM bitcells such as 6T, 8T, 9T, and 10T with PVT
variations. The simulations are carried out in microwind using 90nm technology.
(i) FOUR BIT SRAM CELL DESIGN:
Fig6-fourbit sram cell design fot st-1
Fig7:waveform of st-1 sram cell
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Fig8: fourbit sram cell design fot st-2
Fig9: waveform of st-2 sram cell
Power graph analysis for 4t to 10t sram design cells
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Power graph analysis for ST cells based design
V. Conclusions
Performance comparison of various SRAM bit cells such as 8T, 9T, 10T with the conventional 6T
SRAM cell is performed. It has been shown that in terms of leakage power reduction and energy, ST SRAM cell
has the best performance in comparison to 8T and 9T cells and 10T. In terms of robustness to variation in
temperature.
References
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