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9_DVD_Dynamic_logic_circuits.pdf

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Usha Mehta
Usha Mehta

CMOS, VLSI Design, Dynamic Logic

Engineering
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11/22/2023 Dynamic Logic Circuits 1 Dynamic Logic Circuits Prof . (Dr.) Usha Mehta
11/22/2023 Dynamic Logic Circuits 2 Introduction •In static circuits the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices •Dynamic circuits use temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors
11/22/2023 Dynamic Logic Circuits 3 Advantages and Disadvantages of Dynamic Logic • Advantages • Allow implementation of simple sequential circuits with memory functions. • Use of common clock signals throughout the system enables the synchronization of various circuit blocks. • Implementation of complex circuits requires a smaller silicon area than static circuits. • Often consumes less dynamic power than static designs, due to smaller parasitic capacitances. • Operates at higher speed • Noise Immunity • Disadvantages • Requires clock • Charge Sharing and Charge Leakage • Can not operate at low frequency • Complicated design
11/22/2023 Dynamic Logic Circuits 4 Dynamic Latch • CK = 1: MP turns ON. Cx is charged up or down through MP depending on the input D voltage level. Q = D. • CK = 0: MP turns OFF, and Cx is isolated from input D. Q is determined by charge stored on Cx during previous CK = 1.
11/22/2023 Dynamic Logic Circuits 5 D Latch
11/22/2023 Dynamic Logic Circuits 6 Charge Leakage Problem
11/22/2023 Dynamic Logic Circuits 7 Synchronous Dynamic Circuits
11/22/2023 Dynamic Logic Circuits 8 3-Stage Dynamic Shift Register
11/22/2023 Dynamic Logic Circuits 9 2-Stage Synchronous Complex Logic Circuit
11/22/2023 Dynamic Logic Circuits 10 Dynamic CMOS Transmission Gate Logic
11/22/2023 Dynamic Logic Circuits 11 CMOS Transmission Gate Dynamic Shift Register
11/22/2023 Dynamic Logic Circuits 12 Towards the faster Circuits…. • What makes a circuit fast? • I = C dV/dt -> tpd  (C/I) DV • low capacitance • high current • small swing • In CMOS • Speed is less because of high capacitance of pMOS • In Pseudo-nMOS • The power is high because of continuous current flow through pMOS • Pseudo-nMOS is rationed logic
11/22/2023 Dynamic Logic Circuits 13 A modification to Pseudo-nMOS • Rather than continuous ON load pMOS, use clocked pMOS. 1 2 A Y 4/3 2/3 A Y 1 1 A Y  Static Pseudo-nMOS Dynamic
11/22/2023 Dynamic Logic Circuits 14 Why the foot? • What if pulldown network is ON during precharge? • Use series evaluation transistor to prevent fight. • Further, input should change during the precharge phase, if they change during evaluate phase, charge redistribution can corrupt the output. A Y  foot precharge transistor
11/22/2023 Dynamic Logic Circuits 15 Precharge Evaluate Logic
11/22/2023 Dynamic Logic Circuits 16 Combination Function
11/22/2023 Dynamic Logic Circuits 17 Advantages of PE logic • Requires n+2 transistors compared to 2n transistors in CMOS • Low static power dissipation • No DC current path to restrict the device sizing • Pull up time is improved by active switch to Vdd
11/22/2023 Dynamic Logic Circuits 18 Disadvantages • Output is available only for <50% of time • Pull down time is degraded because of extra Me transistor • Charge sharing problem • Maximum clock frequency is determined by leakage, discharge and delays because of C • Inputs can only change during precharge phase. Inputs must be stable during evaluate.
11/22/2023 Dynamic Logic Circuits 19 ; • Dynamic gates require monotonically rising inputs during evaluation • 0 -> 0 • 0 -> 1 • 1 -> 1 • But not 1 -> 0 A   Precharge Evaluate Y Precharge A Output should rise but does not violates monotonicity during evaluation
11/22/2023 Dynamic Logic Circuits 20 Cascading Issue with Precharge Evaluate Logic
11/22/2023 Dynamic Logic Circuits 21 Domino Logic
11/22/2023 Dynamic Logic Circuits 22 Charge Sharing
11/22/2023 Dynamic Logic Circuits 23 Solutions to Charge Sharing
11/22/2023 Dynamic Logic Circuits 24 Solution to charge Sharing….
11/22/2023 Dynamic Logic Circuits 25
11/22/2023 Dynamic Logic Circuits 26 What about Pre-discharge Evaluate Logic?
11/22/2023 Dynamic Logic Circuits 27 NP Domino/NORA/ZIPPER Logic
11/22/2023 Dynamic Logic Circuits 28 Example
11/22/2023 Dynamic Logic Circuits 29 Summary • Full complementary static logic is best option in the majority of CMOS circuits. • Noise-immunity is not sensitive to kn/kp • Does not involve precharge of nodes • Dissipate no DC power • Layout can be automated • Large fan-in gates lead to complex circuit structures (2N transistors) • Larger parasitics • Slower and higher dynamic power dissipation than alternatives • No clock
11/22/2023 Dynamic Logic Circuits 30 Summary (Cont.) • Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates. • Require only N+1 transistors for N fan-in • Smaller parasitics • Faster and lower dynamic power dissipation than full CMOS • Noise immunity sensitive to kn/kp • Dissipate DC power when pulled down • Not well suited for automated layout • No clock
11/22/2023 Dynamic Logic Circuits 31 Summary (Cont.) • CMOS domino logic should be used for low-power, high speed applications • Require only N+k transistors for N fan-in, size advantages of pseudo-nMOS. • Dissipate no DC power • Noise immunity is not sensitive to kn/kp • Use of clocks enables synchronous operation • Rely on storage on soft node • Require exhaustive simulation at all the process corners to insure proper operation • Some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time.
11/22/2023 Dynamic Logic Circuits 32 Thank You!

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9_DVD_Dynamic_logic_circuits.pdf

  • 1. 11/22/2023 Dynamic Logic Circuits 1 Dynamic Logic Circuits Prof . (Dr.) Usha Mehta
  • 2. 11/22/2023 Dynamic Logic Circuits 2 Introduction •In static circuits the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices •Dynamic circuits use temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors
  • 3. 11/22/2023 Dynamic Logic Circuits 3 Advantages and Disadvantages of Dynamic Logic • Advantages • Allow implementation of simple sequential circuits with memory functions. • Use of common clock signals throughout the system enables the synchronization of various circuit blocks. • Implementation of complex circuits requires a smaller silicon area than static circuits. • Often consumes less dynamic power than static designs, due to smaller parasitic capacitances. • Operates at higher speed • Noise Immunity • Disadvantages • Requires clock • Charge Sharing and Charge Leakage • Can not operate at low frequency • Complicated design
  • 4. 11/22/2023 Dynamic Logic Circuits 4 Dynamic Latch • CK = 1: MP turns ON. Cx is charged up or down through MP depending on the input D voltage level. Q = D. • CK = 0: MP turns OFF, and Cx is isolated from input D. Q is determined by charge stored on Cx during previous CK = 1.
  • 5. 11/22/2023 Dynamic Logic Circuits 5 D Latch
  • 6. 11/22/2023 Dynamic Logic Circuits 6 Charge Leakage Problem
  • 7. 11/22/2023 Dynamic Logic Circuits 7 Synchronous Dynamic Circuits
  • 8. 11/22/2023 Dynamic Logic Circuits 8 3-Stage Dynamic Shift Register
  • 9. 11/22/2023 Dynamic Logic Circuits 9 2-Stage Synchronous Complex Logic Circuit
  • 10. 11/22/2023 Dynamic Logic Circuits 10 Dynamic CMOS Transmission Gate Logic
  • 11. 11/22/2023 Dynamic Logic Circuits 11 CMOS Transmission Gate Dynamic Shift Register
  • 12. 11/22/2023 Dynamic Logic Circuits 12 Towards the faster Circuits…. • What makes a circuit fast? • I = C dV/dt -> tpd  (C/I) DV • low capacitance • high current • small swing • In CMOS • Speed is less because of high capacitance of pMOS • In Pseudo-nMOS • The power is high because of continuous current flow through pMOS • Pseudo-nMOS is rationed logic
  • 13. 11/22/2023 Dynamic Logic Circuits 13 A modification to Pseudo-nMOS • Rather than continuous ON load pMOS, use clocked pMOS. 1 2 A Y 4/3 2/3 A Y 1 1 A Y  Static Pseudo-nMOS Dynamic
  • 14. 11/22/2023 Dynamic Logic Circuits 14 Why the foot? • What if pulldown network is ON during precharge? • Use series evaluation transistor to prevent fight. • Further, input should change during the precharge phase, if they change during evaluate phase, charge redistribution can corrupt the output. A Y  foot precharge transistor
  • 15. 11/22/2023 Dynamic Logic Circuits 15 Precharge Evaluate Logic
  • 16. 11/22/2023 Dynamic Logic Circuits 16 Combination Function
  • 17. 11/22/2023 Dynamic Logic Circuits 17 Advantages of PE logic • Requires n+2 transistors compared to 2n transistors in CMOS • Low static power dissipation • No DC current path to restrict the device sizing • Pull up time is improved by active switch to Vdd
  • 18. 11/22/2023 Dynamic Logic Circuits 18 Disadvantages • Output is available only for <50% of time • Pull down time is degraded because of extra Me transistor • Charge sharing problem • Maximum clock frequency is determined by leakage, discharge and delays because of C • Inputs can only change during precharge phase. Inputs must be stable during evaluate.
  • 19. 11/22/2023 Dynamic Logic Circuits 19 ; • Dynamic gates require monotonically rising inputs during evaluation • 0 -> 0 • 0 -> 1 • 1 -> 1 • But not 1 -> 0 A   Precharge Evaluate Y Precharge A Output should rise but does not violates monotonicity during evaluation
  • 20. 11/22/2023 Dynamic Logic Circuits 20 Cascading Issue with Precharge Evaluate Logic
  • 21. 11/22/2023 Dynamic Logic Circuits 21 Domino Logic
  • 22. 11/22/2023 Dynamic Logic Circuits 22 Charge Sharing
  • 23. 11/22/2023 Dynamic Logic Circuits 23 Solutions to Charge Sharing
  • 24. 11/22/2023 Dynamic Logic Circuits 24 Solution to charge Sharing….
  • 26. 11/22/2023 Dynamic Logic Circuits 26 What about Pre-discharge Evaluate Logic?
  • 27. 11/22/2023 Dynamic Logic Circuits 27 NP Domino/NORA/ZIPPER Logic
  • 28. 11/22/2023 Dynamic Logic Circuits 28 Example
  • 29. 11/22/2023 Dynamic Logic Circuits 29 Summary • Full complementary static logic is best option in the majority of CMOS circuits. • Noise-immunity is not sensitive to kn/kp • Does not involve precharge of nodes • Dissipate no DC power • Layout can be automated • Large fan-in gates lead to complex circuit structures (2N transistors) • Larger parasitics • Slower and higher dynamic power dissipation than alternatives • No clock
  • 30. 11/22/2023 Dynamic Logic Circuits 30 Summary (Cont.) • Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates. • Require only N+1 transistors for N fan-in • Smaller parasitics • Faster and lower dynamic power dissipation than full CMOS • Noise immunity sensitive to kn/kp • Dissipate DC power when pulled down • Not well suited for automated layout • No clock
  • 31. 11/22/2023 Dynamic Logic Circuits 31 Summary (Cont.) • CMOS domino logic should be used for low-power, high speed applications • Require only N+k transistors for N fan-in, size advantages of pseudo-nMOS. • Dissipate no DC power • Noise immunity is not sensitive to kn/kp • Use of clocks enables synchronous operation • Rely on storage on soft node • Require exhaustive simulation at all the process corners to insure proper operation • Some of the speed advantage over static gates is diminished by the required pre-charge (pre-discharge) time.
  • 32. 11/22/2023 Dynamic Logic Circuits 32 Thank You!