This document discusses static timing analysis for combinational circuits. It provides examples of how to represent a combinational circuit as a directed acyclic graph (DAG) with vertices for input/output pins and gates and edges to show connections and delays. It describes how to find the critical path, which is the longest path between input and output, using depth-first search algorithms. The document also discusses false paths that exist physically in a design but are not functional logic paths and how designers typically specify false paths. Homework is assigned to implement an algorithm to find the longest path in a DAG using TCL/TK scripting.