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Verification
Tools
Dr Usha Mehta
usha.mehta@ieee.org
usha.mehta@nirmauni.ac.in
Acknowledgement…..
This presentation has been summarized from various
books, papers, websites and presentations on VLSI
Design and its various topics all over the world. I
couldn’t item-wise mention from where these large
pull of hints and work come. However, I’d like to
thank all professors and scientists who created such
a good work on this emerging field. Without those
efforts in this very emerging technology, these notes
and slides can’t be finished.
2
Dr
Usha
Mehta
25-01-2022
Linting
• It finds common programmer mistake
• It will allow programmer to find mistakes quickly and
efficiently very early instead of at the end waiting for full
programme to fail
• Checks for static errors or potential errors and coding
style guideline violations.
• Static errors: Errors that do not require input
vectors.
• E.g.
• A bus without driver,
• mismatch of port width in module definition and
instantiation.
• dangling input of a gate.
3
Dr
Usha
Mehta
25-01-2022
Simulator
• Most common and familiar verification tool.
• Its role is limited to approximate reality.
• Simulators attempt to create an artificial universe that
mimic the future real design.
• This lets the designer interact with the design before it is
manufactured and correct flaws and problems earlier.
• Functional correctness and accuracy is a big issue as
errors can not be proven not to exist
• Simulator makes a computing model of the circuit,
executes the model for a set of input signals (stimuli,
patterns, or vector), and verifies the output signals.
• Limitations of simulation
• Timing issues with the simulator.
• The simulator can never mimic the real signal where
actual electron flows at a speed of light.
• Can’t be exhaustive for non-trivial designs
• Performance bottleneck
4
Dr
Usha
Mehta
25-01-2022
Simulators
at different abstraction level
• System level –everything electrical, mechanical,
optical etc.
• Behavioral level – algorithm or data flow graph
by HDL
• Instruction set level – for CPU
• Register Transfer level + combinational level
• Gate level – gate as a basic element
• Switch level - transistor as a switch
• Circuit level - current and voltage parameter
• Device level - fabrication parameter
• Timing simulation – timing model
• Fault simulation- checks a test vector for fault
5
Dr
Usha
Mehta
25-01-2022
Waveform Viewer
• It can play back the events that occurred
during the simulation that were recorded in
some trace file
• Recording waveform trace data is a
overburden on simulation and decreases its
performance
6
Dr
Usha
Mehta
25-01-2022
Bug Tracking System (BTS)
• When a bug found by verification
engineer, it is reported ( logged) into BTS
• It sends notification to designer
• Stages:
• Open :When it is filed
• Verified :When designer confirms that it is
bug!
• Fixed :When it is removed from design
• Closed :When everything else works fine with
new fix
• BTS allows project manager to prioritize
the bugs and estimate project progress
report
7
Dr
Usha
Mehta
25-01-2022
Regression and Revision Control
• Regression
• Return to the normal state.
• New features + bug fixes are made available to the
team.
• Revision Control
• When multiple users accessing the same data,
data loss may result.
• e.g. trying to write to the same file simultaneously.
• Prevent multiple writes.
8
Dr
Usha
Mehta
25-01-2022
Verification Language
Hardware Description
Languages
• VHDL, Verilog
• concurrent mechanisms
for controlling traffic
streams to device input
ports, and for checking
outstanding transactions
at the output ports
• but not suitable for
building complex
verification environment
Software
Languages
• C, C++
• Suitable for building
complex environment
• but No built-in
constructs for modeling
hardware concepts such
as concurrency,
operating in simulation
time, or manipulating
vectors of various bit
widths.
9
Dr
Usha
Mehta
25-01-2022
Hardware Verification Languages
• Why Verification languages
• Raised the abstraction level hence productivity
• Can automate verification
• Commercial
• e from Verisity
• Openvera from Synopsys
• RAVE from Forte
• Public domain or open source
• System C from Cadence
• Jeda from Juniper Networks
10
Dr
Usha
Mehta
25-01-2022
System Verilog:
Hardware Description and Verification Language
11
Dr
Usha
Mehta
25-01-2022
Quality of Verification
• What if your testbench itself is buggy?
• Should test bench be verified? How? 12
Dr
Usha
Mehta
25-01-2022
Type I
False Negative
Bad Design
Good Design
Pass
Type II
False Positive
Fail
How to reduce verification time
and efforts?
• Verification is a bottleneck in project’s time-to-
profit goal so verification is the target of new
tools and methodology.
• All these tools and methodology attempts to
reduce verification efforts and time by
1. Parallelism of efforts
2. Higher abstraction level
3. Automation
• Some new concepts are
1. Design for verification
2. Verification of a Reusable Design
3. Verification Reuse (Verification IP –VIP)
13
Dr
Usha
Mehta
25-01-2022
Parallelism of Efforts
• Additional resource applied effectively to
reduce the total verification efforts
• e.g. to dig a hole more workers armed with
shovels
• To be able to write – debug testbenches
parallel to each other as well as parallel to
design implementation.
14
Dr
Usha
Mehta
25-01-2022
Higher Level of Abstraction
• Enables to work more efficiently without worrying
about low level details.
• Reduction in control
• Additional training to understand the abstraction
mechanism and how desired effect is produced.
• To work at transaction levels or bus cycle levels in
stead of dealing with ones and zeroes.
15
Dr
Usha
Mehta
25-01-2022
Automation
• A machine completes the task autonomously
• Faster
• Predictable result
• It requires a well defined inputs and a standard
process.
• When variety of work exists, automation is
difficult.
• Variety of functions, interfaces, protocols and
transformation makes automation in verification
difficult.
• Tools automates various parts of verification
process but not the complete process.
• Randomization of input generation is one way to
automate verification process.
16
Dr
Usha
Mehta
25-01-2022
Design for Verification
• It is reasonable to require additional design effort
to simplify verification.
• Not only should the architect of the design answer
the question
“what is this supposed to do?”
• but also
“how is this thing going to be verified?’
• It includes:
• Well defined interfaces
• Clear separation of functions in relatively
independent units
• Providing additional software accessible registers
to control and observe internal locations
• Providing programmable multiplexers to isolate
or bypass functional units.
17
Dr
Usha
Mehta
25-01-2022
Verification Reuse
• Improving verification productivity is an
economic necessity. Verification reuse directly
addresses higher productivity
• If a bus functional model used to verify a
design block can be reused to verify the
system that uses that block.
• All components be built and packaged
uniformly.
• Verification reuse has its challenges. At the
component level, to reuse the test cases or test
benches is a simpler task but to reuse a test
bench component at different projects or
between two different level of abstraction has
many challenges
18
Dr
Usha
Mehta
25-01-2022
Verification of Reusable Design
• It is proven that design reuse is more
problematic because “ Reuse is about
trust”.
• Functional verification matrix can only give
that trust to design reuser.
• The reusable design should be verified to a
greater degree of confidence than custom
designs
• Reusable designs need to be verified for all
future possible configuration and possible
uses
19
Dr
Usha
Mehta
25-01-2022
25-01-2022
Dr
Usha
Mehta
20
Thanks……

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6 verification tools

  • 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Dr Usha Mehta 25-01-2022
  • 3. Linting • It finds common programmer mistake • It will allow programmer to find mistakes quickly and efficiently very early instead of at the end waiting for full programme to fail • Checks for static errors or potential errors and coding style guideline violations. • Static errors: Errors that do not require input vectors. • E.g. • A bus without driver, • mismatch of port width in module definition and instantiation. • dangling input of a gate. 3 Dr Usha Mehta 25-01-2022
  • 4. Simulator • Most common and familiar verification tool. • Its role is limited to approximate reality. • Simulators attempt to create an artificial universe that mimic the future real design. • This lets the designer interact with the design before it is manufactured and correct flaws and problems earlier. • Functional correctness and accuracy is a big issue as errors can not be proven not to exist • Simulator makes a computing model of the circuit, executes the model for a set of input signals (stimuli, patterns, or vector), and verifies the output signals. • Limitations of simulation • Timing issues with the simulator. • The simulator can never mimic the real signal where actual electron flows at a speed of light. • Can’t be exhaustive for non-trivial designs • Performance bottleneck 4 Dr Usha Mehta 25-01-2022
  • 5. Simulators at different abstraction level • System level –everything electrical, mechanical, optical etc. • Behavioral level – algorithm or data flow graph by HDL • Instruction set level – for CPU • Register Transfer level + combinational level • Gate level – gate as a basic element • Switch level - transistor as a switch • Circuit level - current and voltage parameter • Device level - fabrication parameter • Timing simulation – timing model • Fault simulation- checks a test vector for fault 5 Dr Usha Mehta 25-01-2022
  • 6. Waveform Viewer • It can play back the events that occurred during the simulation that were recorded in some trace file • Recording waveform trace data is a overburden on simulation and decreases its performance 6 Dr Usha Mehta 25-01-2022
  • 7. Bug Tracking System (BTS) • When a bug found by verification engineer, it is reported ( logged) into BTS • It sends notification to designer • Stages: • Open :When it is filed • Verified :When designer confirms that it is bug! • Fixed :When it is removed from design • Closed :When everything else works fine with new fix • BTS allows project manager to prioritize the bugs and estimate project progress report 7 Dr Usha Mehta 25-01-2022
  • 8. Regression and Revision Control • Regression • Return to the normal state. • New features + bug fixes are made available to the team. • Revision Control • When multiple users accessing the same data, data loss may result. • e.g. trying to write to the same file simultaneously. • Prevent multiple writes. 8 Dr Usha Mehta 25-01-2022
  • 9. Verification Language Hardware Description Languages • VHDL, Verilog • concurrent mechanisms for controlling traffic streams to device input ports, and for checking outstanding transactions at the output ports • but not suitable for building complex verification environment Software Languages • C, C++ • Suitable for building complex environment • but No built-in constructs for modeling hardware concepts such as concurrency, operating in simulation time, or manipulating vectors of various bit widths. 9 Dr Usha Mehta 25-01-2022
  • 10. Hardware Verification Languages • Why Verification languages • Raised the abstraction level hence productivity • Can automate verification • Commercial • e from Verisity • Openvera from Synopsys • RAVE from Forte • Public domain or open source • System C from Cadence • Jeda from Juniper Networks 10 Dr Usha Mehta 25-01-2022
  • 11. System Verilog: Hardware Description and Verification Language 11 Dr Usha Mehta 25-01-2022
  • 12. Quality of Verification • What if your testbench itself is buggy? • Should test bench be verified? How? 12 Dr Usha Mehta 25-01-2022 Type I False Negative Bad Design Good Design Pass Type II False Positive Fail
  • 13. How to reduce verification time and efforts? • Verification is a bottleneck in project’s time-to- profit goal so verification is the target of new tools and methodology. • All these tools and methodology attempts to reduce verification efforts and time by 1. Parallelism of efforts 2. Higher abstraction level 3. Automation • Some new concepts are 1. Design for verification 2. Verification of a Reusable Design 3. Verification Reuse (Verification IP –VIP) 13 Dr Usha Mehta 25-01-2022
  • 14. Parallelism of Efforts • Additional resource applied effectively to reduce the total verification efforts • e.g. to dig a hole more workers armed with shovels • To be able to write – debug testbenches parallel to each other as well as parallel to design implementation. 14 Dr Usha Mehta 25-01-2022
  • 15. Higher Level of Abstraction • Enables to work more efficiently without worrying about low level details. • Reduction in control • Additional training to understand the abstraction mechanism and how desired effect is produced. • To work at transaction levels or bus cycle levels in stead of dealing with ones and zeroes. 15 Dr Usha Mehta 25-01-2022
  • 16. Automation • A machine completes the task autonomously • Faster • Predictable result • It requires a well defined inputs and a standard process. • When variety of work exists, automation is difficult. • Variety of functions, interfaces, protocols and transformation makes automation in verification difficult. • Tools automates various parts of verification process but not the complete process. • Randomization of input generation is one way to automate verification process. 16 Dr Usha Mehta 25-01-2022
  • 17. Design for Verification • It is reasonable to require additional design effort to simplify verification. • Not only should the architect of the design answer the question “what is this supposed to do?” • but also “how is this thing going to be verified?’ • It includes: • Well defined interfaces • Clear separation of functions in relatively independent units • Providing additional software accessible registers to control and observe internal locations • Providing programmable multiplexers to isolate or bypass functional units. 17 Dr Usha Mehta 25-01-2022
  • 18. Verification Reuse • Improving verification productivity is an economic necessity. Verification reuse directly addresses higher productivity • If a bus functional model used to verify a design block can be reused to verify the system that uses that block. • All components be built and packaged uniformly. • Verification reuse has its challenges. At the component level, to reuse the test cases or test benches is a simpler task but to reuse a test bench component at different projects or between two different level of abstraction has many challenges 18 Dr Usha Mehta 25-01-2022
  • 19. Verification of Reusable Design • It is proven that design reuse is more problematic because “ Reuse is about trust”. • Functional verification matrix can only give that trust to design reuser. • The reusable design should be verified to a greater degree of confidence than custom designs • Reusable designs need to be verified for all future possible configuration and possible uses 19 Dr Usha Mehta 25-01-2022