The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A high speed low power consumption d flip flop for high speed phase frequency...IAEME Publication
Phase Frequency Detector (PFD) and Frequency divider are indispensable modules of PLL,
which uses D flip-flop as an integral part. This paper focus on design of High-Speed, Low Power
Consumption D Flip-Flop for High Speed Phase Frequency Detector and Frequency divider. The
designed Frequency divider has been used in the divider counter of the phase locked loop. A divide
counter is required in the feedback loop to scales down the frequency of the VCO output signal. The
conventional and proposed D-Flip flop has been designed in UMC 180nm CMOS Technology with
supply voltage 1.8 using CADENCE spectre tool. Virtuoso Analog Design Environment tool of
Cadence have used to design and simulate schematic. This work has been used in the design of 2.4
GHz CMOS PLL targeting Frequency Multiplier application. The proposed D flip flop circuit is
faster than the conventional circuit as it has fast reset operation. The circuit consumes less power as
it prevents short circuit power consumption.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Single-Phase Clock Multiband Low-Power Flexible Dividerijsrd.com
In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.
My first comprehensive wlan presentation in the draft-11n days in 2008.
Note: Lots of text and pictures are used from across the web, author doesn't claim any copyright on them. In case of issues/feedback please email: chaitanya.mgit@gmail.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
Active matrix organic light emitting diode
(AMOLED) displays are considerably attractive for high
brightness, high efficiency and fast response time. Active
matrix employing thin Film Transistors (TFTs) allows
OLED displays to be larger in size, higher in resolution
and lower in power consumption than passive matrix.
Especially, low temperature polycrystalline silicon
(LTPS) TFT employing excimer laser annealing (ELA) is
widely used due to high mobility and high stability. A
number of TFT active matrix pixel circuits have been
developed in order to compensate for TFT parameter
variations due to the fluctuation of excimer laser energy.
We discuss various compensation schemes of LTPS TFT
pixel circuits.
Keywords: AMOLED; poly-Si TFT; pixel
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Design and Analysis of Sequential Elements for Low Power Clocking System with...IJERA Editor
This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.
My first comprehensive wlan presentation in the draft-11n days in 2008.
Note: Lots of text and pictures are used from across the web, author doesn't claim any copyright on them. In case of issues/feedback please email: chaitanya.mgit@gmail.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
Active matrix organic light emitting diode
(AMOLED) displays are considerably attractive for high
brightness, high efficiency and fast response time. Active
matrix employing thin Film Transistors (TFTs) allows
OLED displays to be larger in size, higher in resolution
and lower in power consumption than passive matrix.
Especially, low temperature polycrystalline silicon
(LTPS) TFT employing excimer laser annealing (ELA) is
widely used due to high mobility and high stability. A
number of TFT active matrix pixel circuits have been
developed in order to compensate for TFT parameter
variations due to the fluctuation of excimer laser energy.
We discuss various compensation schemes of LTPS TFT
pixel circuits.
Keywords: AMOLED; poly-Si TFT; pixel
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
4 Channel Relay Board 5V-Bluetooth Compatible for ArduinoRaghav Shetty
Bluetooth technology is a short distance communication technology used by almost all phones
including smart phones and all laptops. This technology find very wide uses including that of Home &
Industrial automation.
The Relay shield is capable of controlling 4 relays. The max switching power could be
12A/250VAC or 15A/24VDC. It could be directly controlled by Arduino through digital IOs.
In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...VLSICS Design
A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
A new improved mcml logic for dpa resistant circuitsVLSICS Design
Security of electronic data remains the major conce
rn. The art of encryption to secure the data can be
achieved in various levels of abstraction. The choi
ce of the logic style in implementing the security
algorithms has greater significance, and it can enh
ance the ability of providing better resistance to
side
channel attacks. The static CMOS logic style is pro
ved to be prone to side channel power attacks. The
exploration of CMOS current mode logic style for re
sistance against these side channel attacks is disc
ussed
in this paper. Various characteristics of the curre
nt mode logic styles, which make it suitable for ma
king
DPA resistant circuits are explored. A new methodol
ogy of biasing the sleep transistors of (MOS curren
t
mode logic) MCML families is proposed. It uses pass
gate transistors for power-gating the circuits. Th
e
power variations of the proposed circuits are compa
red against the standard CMOS counterparts. Logic
gates such as XOR, NAND and AND gate structures of
MCML families and static CMOS are designed and
compared for the ability of side channel resistance
. A distributed arrangement of sleep transistors fo
r
reducing the static power dissipation in the logic
gates is also proposed, designed and analyzed. All
the
logic gates in MCML and CMOS were implemented using
standard 180 nm CMOS technology employing
Cadence® EDA tools.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Minimization of redundant internal voltage swing in cmos full addereSAT Journals
Abstract We proposed a CMOS full-adder cell for low-power applications. The proposed logic structure of CMOS full-adder is used to minimize unnecessary internal voltage swing taken place in the prior CMOS full-adder by adding four nMOS transistors to the logic structure of SUM circuit and three nMOS transistors to the logic structure of CARRY circuit. These nMOS transistors are used to minimize the internal voltage swing from (0VDD) to ((0 - Vtp)VDD) during redundant internal voltage transitions. For area constrain applications, we can use these extra nMOS transistors either to the SUM or CARRY circuit depending upon our need. The proposed full-adder has maximum of 36ps longer data to output delay as compared to the prior CMOS full-adder. The full adder was designed with a 0.18휇m CMOS technology. Index Terms: Delay, dynamic power, full-adder, voltage swing
Minimization of redundant internal voltage swing in cmos full addereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...
3512vlsics05
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
LOW POWER DYNAMIC BUFFER CIRCUITS
Amit Kumar Pandey1, Ram Awadh Mishra2 and Rajendra Kumar Nagaria3
Department of Electronics and Communication, M.N.N.I.T, Allahabad, India
amitkumarpandey1@gmail.com1,ramishra@mnnit.ac.in2,rkn@mnnit.ac.in3
ABSTRACT
In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant
switching at the output node. These circuits prevent propagation of precharge pulse to the output node
during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS
technology. We have calculated the power consumption, delay and power delay product of proposed
circuits and compared the results with existing standard domino circuit for different logic function, loading
condition, clock frequency, temperature and power supply. Our proposed circuits reduce power
consumption and power delay product as compared to standard domino circuit.
KEYWORDS
Buffer, Dynamic circuit, Power consumption, Delay, Precharge pulse.
1. INTRODUCTION
Domino logic circuits are used in wide applications such as microprocessor [1], memory [2],
digital logic [3], etc. It has superior advantage over static logic circuit, it require less number of
transistor count and reduces output load capacitance hence enhance the speed. Realization of
wide fan-in OR gate using static logic circuit requires long stack of PMOS which is not practical,
it increase the delay and area. But domino logic use dual phase namely precharge and evaluation
to implement complex circuit with single evaluation network [4].Domino circuit has drawback of
high power consumption due to clock loading and reduce noise margin due to charge sharing and
charge leakage. Charge sharing is compensated by adding keeper transistor.
Buffer is required to drive the output of the domino logic circuit into the next stage [5]. It is seen
that static logic circuit consume power due to redundant switching at the output node. But domino
logic circuit consumes power due to redundant switching at dynamic and output node [6]. This
redundant switching increase the power consumption. Different techniques are proposed in the
literature to deal this issue. True single phase clock (TSPC) based domino logic [7] and limited
switch dynamic logic (LSDL) [8] reduces the output node redundant switching. TSPC based
domino logic require extra clock transistor, overhead the clock loading. Similarly, latch is added
in LSDL at dynamic node, it increases the area. Power dissipation of the domino circuit is divided
into three components [9]:
DOI : 10.5121/vlsic.2012.3505 53
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
்ܲ௧ = ܲ௬ + ܲ + ܲௌ௧ ௨௧ (1)
PDynamic is the power consumed during capacitance charging and discharging, PLeakage is the total
leakage power of the circuit and this power increases as the technology is scaled down, and PShort
Circuit is the power dissipated when direct current flows from power supply to ground.
ܲ௬ =∝× ܦܦܸ × ܥଶ × ݈݇ܿܨ (2)
Where ∝ is the switching activity at the output and dynamic node, it depends on the gate topology
and inputs, C is the capacitive load at the evaluation node, Fclk is the clock frequency.
ܲ = ܫ × ܸܦܦ (3)
where ILeakage is the combination of subthreshold and gate oxide leakage current.
ܲௌ௧ ௨௧ =∝× ܫௌ × ܸܦܦ (4)
ISC for domino logic gate is the contention current that flows between the evaluation network and
pMOS keeper during evaluation mode. This power dissipation must be kept low for better
operation of the domino circuit.
In this paper, we propose two switching-aware techniques which minimize redundant switching
at the output node. The remainder of the paper is organized as follows. Previous proposed
techniques are described in section 2. Proposed circuits are proposed in section 3. Simulation
results are presented in section 4, and conclusion is presented in section 5.
2. PREVIOUS WORK
Standard domino logic is shown in Fig. 1(a). Operation of the circuit is divided into two phase.
When clock is low, precharge phase, pull up transistor M1 is ON and footer transistor is OFF.
Dynamic node is charged to VDD and output node discharge to zero voltage. Parasitic
capacitance at node F_Node is charged to high. During evaluation phase, M3 is ON, dynamic
node is discharge it depends on the input of the circuit. When input is kept low, dynamic node
maintain high in both operating phase. When input is kept high and operation of the circuit in two
operating phase is characterized in Fig. 1(b).During prechrage phase dynamic node and F_Node
is charge to high voltage and output is discharge to low voltage. During evaluation phase dynamic
and F_Node is discharge to low voltage and output is charge to high voltage [10]. Here
propagation of precharge pulse to the output of the circuit and output logic is unstable. This
redundant switching increase the power consumption.
Circuit techniques have been proposed in the literature such as TSPC based domino logic and
limited switch dynamic logic (LSDL).Main idea regarding these circuit design is to reduce
redundant switching at the output node.
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3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
(a) (b)
Figure 1. (a) Standard domino circuit, (b) Its selected node characteristics.
2.1. Limited switch dynamic logic (LSDL)
Limited switch dynamic logic (LSDL) [8] is shown in Fig 2(a) and its voltage characteristics in
Fig. 2(b). This circuit is similar to the standard domino logic circuit except latch structure is
added at the dynamic node. This latch structure consists of M4, M5, M6, and M7.Transistot M4
and M5 prevents back propagation of the latch signal to the dynamic node. This increases the
parasitic capacitance at the dynamic node and eliminates the redundant switching at the output
node but fails at dynamic node. LSDL provides dual output at OUT1 and OUT2 without the need
of dual rail signalling. There are two drawback of LSDL, first it requires latch circuit to every
dynamic node which increases the power consumption and the area, second it need three clock
transistor which increases the load capacitance of the clock signal.
(a) (b)
Figure 2. Limited switch dynamic logic circuit, (b) Its selected node characteristics [8].
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4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
(a) (b)
Figure 3. (a) TSPC dynamic logic circuit, (b) Its selected node characteristics [7].
2.2. True Single Phase Clock (TSPC) Dynamic Logic
TSPC dynamic logic [7] is shown in Fig. 3(a) and its characteristics at different node is shown in
Fig. 3(b). This circuit is similar to standard footed domino logic except extra nMOS transistor is
connected in the output inverter. This circuit requires 3 clock transistor and it increase the load
capacitance of the clock signal and the power consumption. In this circuit, during precharge phase
transistor M6 is OFF which helps the output to hold its previous value.
3. PROPOSED CIRCUITS
Propagation of precharge pulse during precharge phase in standard domino logic circuit increases
the switching activity at the dynamic node and output node. This increases the power
consumption and output node is unstable. This problem is overcomes by proposed circuit1 and
proposed circuit2. Proposed circuits minimize redundant switching at output node.
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5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
(a) (b)
Figure 4. (a) Proposed circuit 1, (b) Its selected node characteristics.
3.1. Proposed Circuit 1
Circuit diagram of proposed circuit 1 is shown in Fig. 4(a) and its voltage characteristic at
different node is shown in Fig. 4(b) .Implementation of this buffer, consist of extra transistor in
the output inverter as compared to standard domino circuit. This circuit consists of three clock
transistor M1, M3 and M6.The drain of M6 is connected to the dynamic node and its source is
connected to the gate of transistor M5.Using this technique, it avoid precharge pulse not to
propagates to the output node. Operation of this circuit is explained by considering the input
logic. When input logic is low, dynamic node remains high regardless of operating phase and
output node is kept low. When input is high, there are two different cases depending on the
operating phase.
(a) During evaluation phase, dynamic node is discharge to ground. Transistor M4 turns ON and
charges the output node to VDD. On the other hand, high clock turns ON the M6 which turns
OFF the M5.M6 avoid short circuit current in the output inverter.
(b) During precharge phase, pull up transistor M1 turns ON and M3 turns OFF, dynamic node
charged to VDD. Transistor M6 is OFF, which turns OFF the M5 and it helps the output node to
hold the previous value. In this circuit topology, output node is isolated from ground during
precharge phase means it helps to avoid propagation of precharge pulse to the output node.
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6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
3.2. Proposed Circuit 2
Circuit diagram of proposed circuit 2 is shown in Fig. 5(a) and their voltage characteristic at
different node is shown in Fig.5 (b). This buffer is similar to previous circuit except gate of M6 is
connected to F_Node through inverter. Advantage of this circuit is avoiding propagation of
precharge pulse during precharge phase to the output node. Operation of the circuit is explained
by considering the input logic. When input is low, F_node voltage is low, dynamic node remains
high regardless of operating phase and output node is kept low. When input is high, F_Node
voltage is similar to dynamic node voltage, there are two different cases depending on the
operating phase.
(a) During evaluation phase, dynamic node and F_Node is discharge to ground. Output node is
charged to VDD by M4.M6 turns ON due to low voltage at F_Node.M6 pass low dynamic
voltage to the gate of M5, this turns OFF the M5.
(b) During precharge phase, transistor M3 is OFF, pull up transistor M1 precharge the dynamic
node and F_Node is charge to high voltage due to parasitic capacitance at this node. High voltage
at F_Node turns OFF the transistor M6, which turns OFF the M5 and it helps the output node to
hold its previous value.
(a) (b)
Figure 5. (a) Proposed circuit 2, (b) Its selected node characteristics.
4. SIMULATION RESULTS
The proposed circuits are simulated using HSPICE in the high performance 180nm predictive
technology [11].The supply voltage in the simulations is 1.8V and clock rate is 200MHz and with
50% duty cycle (clock period is 5ns) .Rise and fall time of the clock rate is set equal to 10ps.
Transistor size is set by WPMOS =27Lmin, Wp/Wn=2 for whole circuit. Worst case delay is
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7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
determined from input to the output node Vout. Power consumption is determined when input is
high voltage. Standby power is measured when input of the circuit is low.
Comparison of power saving for various logic function of proposed domino circuits with
standard domino circuit is tabulated in Table 1.In this comparison, clock frequency, input
frequency and load capacitance were set to 200MHz,50MHz and 100Ff.From the table, increase
of fan-in, increases the power consumption and OR gate logic consumes more power as compare
to AND gate logic.
Table 1. Comparison of Power Saving with Different Logic Function in 0.18µm (VDD=1.8V,
Clock Frequency=200MHz, Input Frequency=50MHz and load capacitance=100Ff)
Logic Standard Proposed Proposed Power saving by Power saving by
function Circuit circuit 1 circuit2 proposed circuit1 proposed circuit 2
A 46.04 31.86 45.95 30.79% 0.19%
A.B 46.57 33.09 46.00 28.94% 1.22%
A+B 47.17 31.29 42.87 33.66% 9.11%
A.B.C 47.24 34.64 46.50 26.67% 1.56%
A+B+C 48.20 30.97 42.96 35.74% 10.87%
A.B.C.D 47.82 36.30 47.00 24.09% 1.73%
A+B+C+D 49.00 30.93 41.06 36.87% 16.24%
Figure 6. Power versus capacitance. Figure 7. Delay versus capacitance.
Comparison of power consumption of proposed circuits and standard domino circuit with clock
frequency 200 MHz for different loading condition is shown in Fig. 6. As a result, at higher load
capacitance, our proposed circuits save higher power consumption as compared to standard
domino circuit with little delay penalty is shown in Fig. 7 . Our proposed circuits have better
power delay product and at higher load capacitance its saving is large as compared to standard
domino circuit is shown in Fig.8. Proposed circuits also minimize the standby power as compared
to standard domino circuit is shown in Fig.9.
Comparison of power consumption of proposed circuits with standard domino circuit, load
capacitance is set 100fF for different clock frequency is shown in Fig.10. It shows power
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8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
consumption increase as clock frequency increases, maximum power saving is achieved at higher
operating frequency, reduction in power consumption from 37% to 66% at 500MHz clock
frequency compared to standard domino circuit.
Figure 8. Power versus capacitance. Figure 9.Stanby power versus capacitance.
Figure 10. Power consumption versus frequency.
Figure 11. Power versus temperature. Figure 12. Delay versus temperature.
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9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
In Fig.11 illustrates the relationship between the power consumption and temperature for
proposed circuits and standard domino circuit, clock frequency and load capacitance were set
200MHz and 100fF.It shows proposed circuits has much lower power consumption and its value
decrease as temperature increase. For higher temperature our proposed circuits perform better
than standard domino circuit. Similarly, in Fig.12 delay versus temperature is represented. Delay
is linear function of temperature. Our proposed circuits suffer little delay penalty as compared to
standard domino circuit. Fig.13 shows PDP versus temperature, our proposed circuits have
minimum PDP.
Fig.14 illustrated the power consumption for proposed circuits and standard domino circuits for
different supply voltages. The clock frequency is set 200MHz and load capacitance is set
100Ff.Our proposed circuits shows better power saving at higher power supply.
Figure 13. PDP versus temperature. Figure 14. Power versus power supply.
A ripple carry adder is also simulated by using proposed circuit1 and proposed circuit2 is shown
in Fig. 15 and Fig.16. Comparison of power consumption of proposed circuits adder and standard
domino circuit adder for different loading condition, clock frequency is set 200 MHz is
summarized in Table 2.Indicating about 8% to 40% power saving at higher load capacitance.
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10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
Figure 15. 1 bit ripple carry adder using proposed circuit1.
Figure 16. 1 bit ripple carry adder using proposed circuit 2.
Table 2. Comparison of Power Consumption of Proposed Adder Circuits and Standard Domino
Adder Circuit (Clock Frequency=200 MHz and Load Capacitance=100Ff)
Load capacitance(fF) Standard adder Proposed circuit 1 Proposed circuit 2
adder adder
100 69.73 60.664 65.95
200 105.82 76.34 100.35
300 140.32 92.46 132.98
400 175.29 108.40 171.15
500 208.94 123.78 191.44
The layout of the standard domino circuit, proposed circuit 1 and proposed circuit 2 are
implemented using 0.18um standard CMOS technology, have been plotted in Fig.17. Simulation
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11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
results of Pre-layout and post –layout, clock frequency and load capacitance were set 200MHz
and 100fF are summarized in Table.3. From the table, post layout simulations the delay, power
consumption and power delay product reduces as compared to pre-layout simulation. Our
proposed circuits require larger area as compared to standard domino circuit is given in Table 4.
(a) (b) (c)
Figure 17. Layout (a) standard domino circuit. (b) Proposed circuit 1. (c) Proposed circuit 2.
Table 3. Pre- and Post-Layout Simulations Results for Power, Delay and PDP of Standard
Domino Circuit, Proposed Circuit 1 and Proposed Circuit 2 for 0.18µm Standard CMOS
Technology.
Type Delay(ps) Power(µW) PDP(fJ)
Standard domino circuit 683.43 46.04 31.46
Pre-Layout Proposed circuit 1 684.96 31.86 21.82
Proposed circuit 2 685.51 45.45 31.15
Standard domino circuit 672 43.51 29.23
Post-Layout Proposed circuit 1 673.2 29.36 19.76
Proposed circuit 2 694.76 42.1 29.24
Table 4. Area Comparison of Proposed Circuits and Standard Domino Circuit.
Standard domino Proposed Proposed
Area(µm2) circuit circuit 1 circuit 2
37.02 89.6832 47.11
5. CONCLUSIONS
In this paper, two new buffer circuits are proposed. The main idea of using these circuits to
minimize the redundant switching at the output node and saves power as compared to standard
domino circuit. These circuits solve the problem of propagation of precharge pulse during
precharge phase in standard domino circuit. Proposed circuits and standard domino circuit are
simulated in 0.18µm using HSPICE. Performance of the proposed structure is compared with
standard domino circuit for different clock frequency, loading condition and temperature.
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12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012
Carry adder circuit is also simulated by using proposed circuit techniques and standard domino
circuit. Result shows maximum power saving for different loading condition as compared to
standard domino circuit. Layout of proposed circuits and standard domino circuit are
implemented using standard CMOS technology. Post-layout simulation reduces the delay, power
consumption and power delay product as compared to pre-layout simulation.
ACKNOWLEDGEMENTS
The authors duly acknowledge with gratitude the support from ministry of communications and
information technology, DIT Govt. of India, New Delhi, through special Manpower Development
Program in VLSI and related Software’s Phase-II (SMDP-II) project in E&CE department,
MNNIT Allahabad-211004, India.
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AUTHORS
Amit Kumar Pandey is presently Research Scholar in the department of
Electronics and Communication Engineering, M.N.N.I.T, Allahabad, India. He
has 7 years of teaching experience. His research area is low power VLSI circuits.
Dr. R. A. Mishra is presently working as Associate Professor in the Department of
Electronics and Communication Enginnering, M.N.N.I.T Allahabad (U.P) India.
He has 20 years teaching experience and published many papers in International
Journal and Conference proceeding. His research area includes VLSI circuit,
semiconductor devices and modeling and residue number system based circuit
design.
Dr. R. K. Nagaria is an Associate Professor in the department of Electronics and
Communication Engineering, M.N.N.I.T, Aallahabad, India. He received B.Tech
and M.Tech in Electronicss Engineering from Kamla Nehru Institute of
Technology (KNIT) Sultanpur, India and Ph.D. (Engg.) from Jadavpur University,
Kolkata, India. He has been 24 years of teaching and research experience. He has
published more than sixty five research papers of National and International
Conferences/Journals. His name is enlisted in an exclusive directory Marquis
Who’s Who in the world. He is also nominated for the award as International
Educator of the year 2005, by International Biographical Centre, Cambridge
England. He has chaired the technical session in World Congress on Science, Engineering (WCSET-2009),
Oslo (Norway). His area of interest is Mixed-mode/Analog signal processing, high speed networks and
VLSI Design and applications.
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