7_DVD_Combinational_MOS_Logic_Circuits.pdf

11/22/2023 CMOS Combination Design 1
CMOS
Combinational Logic Design
Prof. (Dr.) Usha Mehta
usha.mehta@nirmauni.ac.in

Parameters:
• Depending on the application, the emphasis will be on different metrics
(e.g.,). In addition to these
metrics, robustness to noise is also a very important consideration.

Parameters/Specifications
• Boolean Function : combinational logic (or non-regenerative)
circuits that have the property that at any point in time, the output
of the circuit is related to its current input signals by some Boolean
expression
• Speed: in high performance processor, the switching speed of
digital circuits is the primary metric
• Power : In a battery operated circuit, the energy and power
dissipation is major concern
• Area
• Noise Margin

Static CMOS Design
• CMOS advantages:
• Full swing output: Robustness to noise
• No steady state power
• High performance
• Static Design: static circuits in which at every point in
time (except during the switching transients), each gate
output is connected to either VDD or Vss via a low-
resistance path. Also, the outputs of the gates assume
at all times the value of the Boolean function
implemented by the circuit (ignoring, once again, the
transient effects during switching periods)

Before we start……
• Logic with Switching Circuits….
• Logic can be done with switches
as well as gates.
• A parallel connection implements OR. A series connection
implements AND. Series and parallel combinations can do
complex logic.
• Loop Analysis
• Construct all paths between a logic “1” and the output. Each
path is a string of ANDs. which are ORed together. The
expression comes out as a Sum-of-Products (Σ of Π)
• Cut-Set Analysis
• Make all the cuts that completely separate the output and
Vcc.The cuts must only pass through switches. The switches
in the cut are ORed together. The expression comes out as a
Product-of-Sums (Π of Σ)

In case you forgot…..

Switch Model

MOS as Switch

Pull Up / Pull Down

nMOS-Pull Down
pMOS-Pull Up

Pull Up / Pull Down…..
• For nMOS
• Vgs >= Vtn
• Vg-Vs>=Vtn
• Vsmax = Vg-Vtn i.e. ( 0 to Vg-Vtn only, never Vg=VDD full
is coming to Vs)
• For pMOS
• Vgs =< Vtp
• Vg-Vs =< Vtp
• Vsmin = Vg-Vtp i.e. ( Vtp to Vg only, never Vg=0 is coming
to Vs)

CMOS Inverter

Determine the logic….

Logic to Voltages

Source and Drain Terminals

nMOS-pMOS/Series-Parallel

NAND2

NAND2…

NAND2 & NOR2

Comparisons of CMOS NOR/NAND with
inverter
• Similarity
• Rail-to-rail output swing
• No static power dissipation
• Differences
• DC voltage transfer characteristic
• Noise Margin
• These two are complicated as it depends on data
input patterns

VTC of CMOS NAND2
1. A=0, B=0 A=0->1, B=0->1 A=1, B=1
2. A=0, B=1 A=0->1, B=1 A=1, B=1
3. A=1, B=0 A=1, B=0->1 A=1, B=1

Let’s understand the difference in VTC
• The difference between VTC1 and VTC2 or VTC3 is
because of strong pull up network of two pMOS
conducting together.

Let’s understand the difference in VTC
• The difference between VTC2 and VTC3 is because of
the location difference M1 and M2
• When M1and M2 both are on, the M2 has a body effect
because of VB2=0V, VS2=VDS1
• Thus switching characteristic of M1 is better than

Which is better?
NAND or NOR? Why?
• Considering propagation delay….
• Do remember
• For pMOS and nMOS :
• Hence nMOS is speedier than pMOS.
• So overall delay of CMOS is delay of pMOS
• So to reduce the delay of pMOS, reduce the Ron of pMOS
and hence widen the pMOS i.e. double size.
• R 1/IDD , IDD W/L => R 1/(W/L)

Which is better?
NAND or NOR? Why?
• Now using inverter model,
• Delay
• For NAND
• Worst case rise time delay is
• Worst case ( and only) fall time delay is
• For NOR
• Worst case (and only) rise time delay is :
• Worst case fall time delay is:
• Consider Rn = 1 Unit, analyse delay for NOR
and NAND
• in case of pMOS and nMOS of equal size
• Consider widening of pMOS

Gates with large Fan-ins
• The earlier slide’s analysis draws the attentions
towards the deficiency of CMOS for large Fan-in gates
• Larger Fan-ins means
• Either the series connected pMOSes or nMOSes
• Large difference in rise time and fall time
• Need to find out solutions..

Solution 1
Transistor Sizing

Solution 2
Progressive Transistor Sizing

Solution 3
Transistor Ordering

Primitive Gates
• INVERTER, NAND, NOR
• AND, OR
• What about XOR, XNOR?
• Draw transistor level Schematic

Six Transistors XOR-XNOR

Tristate

Tristate Inverter

COMPLEX Boolean
FUNCTIONS AND ITS
TRANSISTOR LEVEL
SCHEMATIC

Complimentary Static CMOS Gates
• At any time, the output is connected to either
power supply or ground with low resistance
path.
• Conduction of Pull-up network (PUN)and Pull-
down network (PDN) should be mutually
exclusive. (Why?)
• PDN and PUN are dual.
• Complimentary static CMOS are inverting.

Implementation of Combinational Logic

CMOS Topology AOI/OAI

DO REMEBER
• Find and simplify F’
• Make sure that complements are down to the literal level.
• Implement F’ as nMOS net and connect it between
ground and output
• OR operations by parallel connected nMOS
• AND operations are series connected nMOS
• Find dual of F’, implement it as pMOS net and connect
it between output and power supply.
• AND operations by parallel connected pMOS
• OR operations are series connected pMOS

Optimize the transistor level schematic
for # of transistor
• F’
• F
• Literals are available in normal form only
• Literals are available in normal form and complement
form.

Stick Diagram for CMOS Combinational
Circuits

CMOS Structure

gate
drain
source
nMOS Layout
polysilicon
metal
Contact holes
diffusion (active
region)

Stick Diagram
• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers
• Estimate area by counting wiring tracks and other areas
Vin
Vout
VDD
GND

Stick Diagram Colour Notation
Silicon layers are typically colour coded as follows :
This colour representation is used during mask layer definition
Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward
diffusion (device well, local interconnect)
polysilicon (gate electrode, interconnect)
metal (contact, interconnect)
contact windows
depletion implant
P well (CMOS devices)

Layer contact mask layout representation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Metal contacting diffusion
Metal contacting polysilicon
Metal contacting diffusion (no contact, electricall
isolated
with thick oxide)
Metal crossing polysilicon (no contact, electrically
isolated
with thick oxide and so can carry separate voltages)
diffusion
polysilicon
metal
contact windows
depletion implant
P well

Transistor Mask Layout
Preparation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Depletion mode transistor (extra well implant to
provide Vth  -0.6Vdd )
Enhancement mode transistor (Vth  0.2Vdd )
diffusion
polysilicon
metal
contact windows
depletion implant
P well

nMOS transistor coloured
stick diagram

nMOS Inverter Stick Diagram

CMOS Inverter

Static CMOS NAND2 Gate
Stick Diagram

Static NOR2 Gate
Stick Diagram

Static CMOS Design Example Layout

Layout 2 (Different layout style to previous but same function being
implemented)

Two Stick Diagrams of F = (C*(A+B))’
A B C
X
VDD
GND
X
C
A B
VDD
GND
uninterrupted diffusion strip
crossover requiring vias

To construct a minimum area layout…
• For a complex logic function, if we choose arbitrary
ordering of polysilicon gates column:
• The separation between the polysilicon columns must
allow
• Diffusion to diffusion separation
• Diffusion to metal separation
• Hence, to reduce the number of diffusion area break,
the ordering of gate column should be properly
planned.

Let’s try…..
• F=(A(D+E)+BC)’

Stick Diagram

Euler Path
• Find a common Euler path for both p and n graphs
• Euler Path:
• Uninterrupted path which traverse each edge of the graph
exactly once.

p-NET and n-NET

Euler’s Path

Stick Diagram as per Euler’s path

Euler’s Theorem

Euler’s Theorem
B
A D
VDD
GND
C
X

Let’s have one magic!!!!!
• Pl. find the Euler path for x = !(a + bc + de)
• Ok…..
• Now try x = !(bc + a + de)

Duality of Function
• Pl. find Euler’s path for
• F=!(AB+BC+CA)
• Now try with duality concept….
• F = dual of F
• Now pl. check the n and p graph and find the Euler’s
path
• So easy to draw the stick diagram…

Transistor level Schematic of Full Adder

LAYOUT
(W/L is a big concern here!)

CMOS Inverter Mask Layout (using Microwind)
diffusion
polysilicon
metal
contact windows
depletion implant
P well

Static CMOS NOR2 gate

CMOS NAND2 Mask Layout
diffusion
polysilicon
metal
contact windows
depletion implant
P well

Layout Design rules & Lambda ()
• Lambda () : distance by which a geometrical feature or any one layer
may stay from any other geometrical feature on the same layer or any
other layer.
• All processing factors are included plus a safety margin.
•  used to prevent IC manufacturing problems due to mask
misalignment
• or exposure & development variations on every feature, which
otherwise could lead to :
• over-diffusion
• over-etching
• inadvertent transistor creation etc
•  is the minimum dimension which can be accurately re-produced on
the silicon wafer for a particular technology.

• Minimum photolithographic dimension (width, not separation) is
2.
• Hence, the minimum channel length dimension is 2.
• Where a 0.25m gate length is quoted,  is 0.125 microns (m).
• Minimum distance rules between device layers are used, e.g.,
• polysilicon  metal
• metal  metal
• diffusion  diffusion and
• minimum layer overlaps
• Layout design rule checker (DRC) automatically verifies that no
design rules have been broken
• Note however, the use of Lambda is not optimal but supports
design reuse

Lambda based design: half of technology since 1985. As technology
changes with smaller dimensions, a simple change in the value of  can
be used to produce a new mask set.
6
2
6

4
Hcmos6 technology : =0.2µm
Hcmos8 technology : =0.1µm
All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3

Basic Design Rules
• Minimize spared diffusion
• Use minimum poly width (2) •1 contact = 1mA
•Multiply contacts
2mA

Basic Design Rules
• Same N and P alters symmetry • L min
• Wpmos=2 Wnmos
Width of pMOS
should be twice the
width of nMOS

Calculation of Size
Basically calculation of
W/L……..
all other size is with
reference to W/L

Design Strategy
• Fan-out, Rise time, Fall time…
• Load Current, VOL, VOH..…
• Depends on W/L and other parameters…
• Designable parameter is (W/L).
• Find the worst case of above parameters and design for
that (W/L)

• Performing a manual analysis of the dynamic
behavior of complex gates is only tractable via a switch
model.
• Here, the transistor is modelled as a switch with an
infinite off-resistance and a finite on resistance, Ron.
• Ron is chosen so that the equivalent RC-circuit has a
propagation delay identical to the original transistor-
capacitor model.
• Ron is inversely proportional to the W/L ratio but
varies during the switching transient.
• Deriving propagation delay can be done by analysing
the RC network.

W/L Equivalent
(Resistive Load Model)
𝑊
𝐿 𝑒𝑞𝑖
= ෍
𝑘(𝑜𝑛)
𝑊
𝐿 𝑘
𝑊
𝐿 𝑒𝑞𝑢𝑖
=
1
σ𝐾(𝑜𝑛)
1
(𝑊/𝐿)𝑘

Calculate (W/L)equivalent for
resistive load implementation of
F=!(A(D+E)+BC)

Let’s try…..
• Calculate (W/L)equivalent for CMOS implementation
of F=!(A+D+E)(B+C) assuming (W/L)n = 10 and
(W/L)p=15

Various VOL Values

To calculate W/L….
• Specify maximum allowable VOL value
• Calculate equivalent (W/L)driver using for that VOL
• Determine worst case path (class-1)
• Determine worst case path transistor size to give the
equivalent worst path VOL same as equivalent
(W/L)driver

Layout Optimization
Device Folding / Fingering & Sharing
• When we have to make the devices for large current
(like drivers), the width of the devices should be very
high compared to the other devices
• Large transistors can be split into smaller ones and
then shorting the corresponding terminals making up
the required W/L
• In such an arrangement we can share the diffusion
drain and source of adjacent transistors and then we
can short the terminals

Folding & Sharing (Cont...)
Why to have folding / fingering?
➢Poly resistance is reduced as single poly is divided in
multiple parts of poly
➢To maintain the uniformity in diffusion area
➢Process variations are less
Why to have sharing?
➢To save the diffusion area
➢To reduce the parasitic associated with the devices

Transistor Folding

Folding

Sharing…..

Static CMOS
Do remember…
• Every point in time, gate output is connected to either
supply or ground via low resistance path
• Rail to rail output voltage
• Ratioless design
• Low output and Extremely High input impedance
• No static power dissipation
• Good Noise Margin
• BUT what about Rise and Fall Time????

• The complementary CMOS circuit style falls under a
broad class of logic circuits called static circuits in
which at every point in time (except during the
switching transients), each gate output is connected to
either VDD or Vss via a low-resistance path.
• Also, the outputs of the gates assume at all times the
value of the Boolean function implemented by the
circuit (ignoring, once again, the transient effects
during switching periods). This is in contrast to the
dynamic circuit class, that relies on temporary storage
of signal values on the capacitance of high-impedance
circuit nodes. The latt r approach has the advantage
that the resulting gate is simpler and faster. On the
other hand, its design and operation are more involved
than those of its static counterpart, due to an
increased sensitivity to noise.

Static CMOS
Do remember………

Gates with a fan-in greater than 4 become excessively slow and must be
avoided.
Solutions????

Pseudo nMOS Gates
• Only single pMOS in load, permanently gate of pMOS
connected to ground
• Disadvantages:
• Always on load i.e. steady state current, static power
• o/p voltage < Vdd
• Ratioed logic

Ratioed Logic

Pass Transistor
• Strength of signal
• How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• What if source > 0, gate >0 ?
• e.g. pass transistor passing VDD
• Let Vg = VDD
• Now if Vs > VDD-Vt, Vgs < Vt
• Hence transistor would turn itself off
• nMOS pass strong 0
• But degraded or weak 1
• pMOS pass strong 1
• But degraded or weak 0
• NMOS pass transistors pull-up no higher than VDD-Vtn
• Called a degraded “1”
• Approach degraded value slowly (low Ids)
• PMOS pass transistors pull-down no lower than Vtp
• Called a degraded “0”
VDD
VDD
22-11-2023
Dynamic Logic Usha Mehta
105

Pass Transistors
• Transistors can be used as switches
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
22-11-2023
106

But do remember….
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Vs
= VDD
-Vtn
VSS
Vs
= |Vtp
|
VDD
VDD
-Vtn VDD
-Vtn
VDD
-Vtn
VDD
VDD
VDD
VDD
VDD
VDD
-Vtn
VDD
-2Vtn
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107

Logic Functions using Pass Transistors
• As nMOS (or even pMOS)
acts as a switch, we can
implement any Boolean
Function using them.
• Primary inputs drive the
gate terminals +
source/drain terminals.
• In contrast to static
CMOS –primary inputs
drive gate terminals.
• With one nMOS
only….What is the
function?
A
B
Z = ?
22-11-2023
Dynamic
Logic
Usha
Mehta
108

Examples….
• 2:1 MUX
• Using gate level implementation in CMOS:
• 20
• Using transistor level implementation in CMOS:
• 10
• Using pass transistor:
• 04
4
4
D1
D0
S Y
4
2
2
2 Y
2
D1
D0
S
22-11-2023
109

Shannon’s Expansion to implement
Boolean Function
• Theorem: An arbitrary logic function f (x1, x2, …, xn) is
expanded as follows:
f = xi ’f0 + xi f1
f0 = f(x1, x2, …, xi-1, 0, xi+1, …, xn-1, xn)
f1 = f(x1, x2, …, xi-1, 1, xi+1, …, xn-1, xn)
f0 and f1 are “cofactors” of f
NOTE: Although this theorem is named after Claude
Shannon who made the extremely insightful observation
that Boolean algebra could be used to model switching
circuits, the theorem was actually presented by
mathematician George Boole in 1854.
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110

Complimentary Pass Transistor Logic
• To accept and produce true and complimentary inputs
and outputs
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111

CPL Gates
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Dynamic
Logic
Usha
Mehta
112

CPL….
• Since circuit is differential, complimentary inputs and
outputs are available. Although generating differential
signals require extra circuitry, complex gates such as
XORs, MUXs and adders can be realized efficiently.
• CPL is a static gate, because outputs are connected to
Vdd or GND through a low-resistance path (high noise
resilience).
• Design is modular – all gates use same topology; only
inputs are permuted. This facilitates the design of a
library of gates.
22-11-2023
113

NAND 4 Lay out
• Design is modular….
114 Pass Transistor Usha Mehta 22-11-2023

Comparison of Pass Transistor with
CMOS
• The presence of the switch driven by B is
essential to ensure that the gate is static – a
low-impedance path must exist to supply rails.
Adv.:
• Fewer devices to implement some functions.
• Example: AND2 requires 4 devices (including
inverter to invert B) vs. 6 for complementary
CMOS (lower total capacitance).
Disadv.:
• NMOS is effective at passing a 0, but poor at
pulling a node to Vdd. When the pass transistor
a node high, the output only charges up to Vdd-
Vtn. This becomes worse due to the body effect.
The node will be charged up to Vdd – Vtn (Vs)
22-11-2023
115

Main Problem on NMOS only Switches
• VB does not pull up to 2.5V, but 2.5V -VTN
• Threshold voltage loss causes
• static power consumption
• slower transition
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Solution:1
Level Restoring Transistor
• Advantage: Full Swing. Eliminates static power in inverter
+ static power through level restorer and pass transistor,
since restorer is only active when A is high.
• Restorer adds capacitance, takes away pull down current
at X – contention between Mn and Mr (slower switching).
Hence Mr must be sized small. Mn and Mr must be sized
such that the voltage at node X drops below the threshold
of the inverter VM, which is a function in the sizes of M1
and M2.
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117

Solution:2
Pass Transistor with Lower VT
• Use very low threshold
values for NMOS pass
transistors, and standard
high threshold devices for
inverters.
DisAdv.: Leakage Current
• While these leakage paths
are not critical when the
device is switching
constantly, they do pose a
large energy overhead
when the circuit is in the
ideal state.
22-11-2023
118

Solution: 3
Voltage Bootstrapping
• This technique is being used to overcome the thresold
voltage drop in Pass Transistor gates or enhancement load
logic gates
• Let’s consider the enhancement load inverter,
• if Vx is increased to Vdd + Vth then Vout will be Vdd.
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119

Voltage Bootstrapping
• Do you remember voltage double or voltage
trippler using diodes and capacitors?
• i.e. Diode and capacitors can increase the
voltage level!!!!
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120

Solution: 4
Pass Gate/Transmission Gate
• NMOS passes a strong “0” but degraded “1”
• PMOS passes a strong “1” but degraded “0”
• Transmission gates enable rail-to-rail swing
• These gates are particularly efficient in
implementing MUXs
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Pass Gate
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Equivalent Resistance of Pass Gate
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123

22-11-2023
Dynamic
Logic
Usha
Mehta
124

22-11-2023
125

Transmission Gate 2:1 MUX
• NonRestoring:
• Noise on A is passed on to Y (after several stages,
the noise may degrade the signal beyond
recognition)
• Nonrestoring mux uses two transmission gates
• Only 4 transistors
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126

Transmission Gate 4:1 MUX
• 4:1 mux chooses one of 4 inputs using two selects
• Two levels of 2:1 muxes
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Inverting MUX
• Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
• Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
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XOR Gate using Pass Gate Topology
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Complimentary Pass Gate Logic
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Which function is implemented here?
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131

7_DVD_Combinational_MOS_Logic_Circuits.pdf

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