IC Fabrication Process Overview

11/22/2023 IC Fabrication Process 1
IC Fabrication
Prof. (Dr.) Usha Mehta

Acknowledgement
This presentation has been summarized from various
books, papers, websites and presentations on VLSI
Design and its various topics all over the world. I couldn’t
remember where these large pull of hints and work come
from. However, I’d like to thank all professors and
scientists who created such a good work on this emerging
field. Without those efforts in this very emerging
technology, these notes and slides can’t be finished.
NOTE: The figures, text etc included in slides are
borrowed from various books’ websites, authors’ books,
websites, pages and other sources for academic purpose
only. The instructor does not claim any originality.

Clean Room
• As circuit devices are extremely small, any small
impurity atom can damage the component i.e.
transistors in the circuit.
• Hence all the activities of IC fabrication is done in
Cleanroom. A cleanroom is a controlled
environment where pollutants like dust, airborne
microbes, and aerosol particles are filtered out in
order to provide the cleanest area possible.

Cleanroom Classifications
• Depending upon the capacity of cleanliness, the
cleanroom is classified in various category.
• https://www.youtube.com/watch?v=pejjgTlBcVo

Materials used in IC
Within IC
• Doped semiconductor : as base, or Substrate ( wafer)
• Doped Semiconductor: as source, drain, channel-stop
implants etc
• Oxide : for isolation purpose
• Polycrystalline Semiconductor: for making gate
• Metals: for gate, interconnects, I/O pad bonding
• Packaging
For various processing steps, many chemicals are
used.

IC Fabrication
:Doped Semiconductor
• Semiconductor Material: Si or Ge
• Why Si is preferred over Ge as substrate material?
• Less temperature dependency
• Less leakage current
• Less effect of external noise on final device
• Easily available in nature

Doped Semiconductor
• Doping density
• p+, p++, n+, n++ etc for source, drain and channel-
stop implants
Mostly….
• P+ = 10^18 / cm3
P = 10^15 / cm3
• P-=10^13 / cm3
Why p+ for source and drain?
• Source-substrate junction, drain-substrate
junction
• p+ is used to decrease the width of junction in
source or drain region compared to substrate
region.

Polysilicon
• As gate
• Acts as metal for short length of wires
• Very high melting point ( nearly 1400 degree)
compared to metal
• So ease in fabrication as it does not melt during
process
• Provides lower threshold at smaller geometry
• But further scaling not possible with poly gate very
thin poly gate may cause the higher leakage current
because of quantum mechanical tunnelling.

Metal
As interconnect
• Earlier: Aluminium
• Comparatively high resistive but does not diffuse in Si
or SiO2 like Copper
• Also high immunity towards oxidation when exposed.
• Now: Copper
• To achieve speed, Low K metal
As Gate
• High K material to provide better dielectric with very
less width.
For wire bonding
• Pure gold for IO pads to pin bonding

Why gold for wire bonding?
• Conductivity Silver (105) > copper (100)> gold (70)
• Gold , unlike copper and silver, does not tarnish.
• Because silver and copper tarnishes, it is less desirable
for high frequencies because the exterior surface
becomes less conductive.

CMOS
• pMOS and nMOS
• pMOS : n-type substrate
• nMOs: p-type substrate

• n-well
• p-substrate for nMOS and n-well for pMOS
• p-well
• n-substrate for pMOS and p-well for nMOS
• Which one is preferred? Why?
• Twin Tub:
• n substrate
• n well for pMOS as well as p well for nMOS
• To provide separate optimization for
threshold voltage, body effect, gain etc.
n-well, p-well, twin-tub

Which Substrate?
( p-type or n-type wafer)?
• p-type
• nMOS in substrate
• pMOS in n-well
• substrate is to be
reverse-biased by
applying ground
• pMOs is in well so
performance of
pMOS degraded.
• n-type
• pMOS in substrate
• nMOS in p-well
• substrate is to be
reverse-biased by
applying supply
• pMOs is in substratel
so performance of
pMOS not degraded.

Why p-type substrate?
• General CMOS contains both pMOS and nMOS
• But speed critical components are made of nMOS only
and will require less processing steps in p-type wafer
as well as less degradation of nMOS compared to if
they are grown in p-well in n substrate.
• To reverse bias p substrate, the ground is connected
which is better choice from designer’s point of view
compared to n-type wafer being connected to supply
voltage for reverse baising.

n-well CMOS Structure

Making of IC

Making Wafer
1. Purified polycrystalline silicon is created from the
sand
2. Heated to produce molten liquid
3. A small seed silicon doped in liquid and slowly
pulled out from the melt. This will form single
crystal ingot of Si.
4. Thin round wafer of thickness .01 to 0.025 inches is
sliced
5. Smoothened by polishing
6. Cleaned and dried using high purity low particle
chemicals.

Czochralski method for Ingot
Growth
• https://www.youtube.com/watch?v=2qLI-NYdLy8

Wafer Preparation : Czochralski
method
• Si used for crystal growth is
purified from SiO2 (sand)
through refining, fractional
distillation and CVD.
• The raw material contains < 1
ppb impurities. Pulled crystals
contain O (» 1018 cm-3) and C (»
1016 cm-3), plus any added
dopants placed in the melt.
• Polysilicon material is melted,
held at close to 1417 °C, and a
single crystal seed is used to
start the growth.
• Pull rate, melt temperature and
rotation rate are all important
control parameters.

Silicon Structure Millar Indices and Wafers
• Wafer: 10 cm to 30 cm (~4 to ~12 inches) and 1 mm
thick.

Why <100> P type substrate is
preferred?
• <100> allows the maximum efficient ion
implantation because of its orientation

Epitaxial growth
• Epitaxial layer is grown on
surface of wafer for better
material characteristics and
proper formation of CMOS
• P-type substrate is doped
with as much boron as
possible to minimize
substrate resistivity
• Lightly doped p-type
epitaxial layer is grown on
substrate
• nMOS transistors are
formed directly on the epi
layer which serves as back
gate

Oxidation
• Thermal Oxidation for IC fabrication
• Note that the deposition of silicon dioxide (e.g. by
CVD) is not called oxidation.
• The term “oxidation” is used only for converting
existing layer of silicon to silicon dioxide. Thus, it is
a modification process.
• We take silicon and modify it to get silicon dioxide.
• In that sense, it is similar to doping where N- type
or P-type material is added to silicon and modify it.
• Wet Oxidation
• uses water vapour
• Dry Oxidation
• uses high-purity oxygen and hydrogen at ~1000
degrees C.

Oxidation
• SiO2 growth consumes silicon, grows into the
substrate.
• SiO2 is twice the volume of Si, projects above the
substrate as well.
• The oxidation occurs at the silicon and the silicon
dioxide interface that is the oxidizing species
whether it is oxygen or stream has to diffuse
through already existing silicon dioxide

• Now on substrate, we want to create different
regions like n-well, source, drain, polysilicon gate,
contacts, interconnects etc…
• For creation of each such area on substrate, i.e the
process of creating n, n+, p+, oxide growth,
metallization etc…some major steps are repeated
each time.

Lithography
• IC: a set of patterned layers of doped silicon,
polysilicon, metal and insulating dioxide.
• A layer must be patterned before the next layer of
material is applied on the chip.
• A process used to transfer a pattern to a layer on the
chip is called Lithography.
• Each layer has its own patterning requirement.
• This pattern is defined in a Mask

Mask Set
• Transistors and wires are defined by Mask
• Cross section taken along dashed line

Detailed
Masks

Patterning
• To protect some areas of wafer when working on
another area
• Process called lithography
• In each processing step, regions are selected for
processing using lithography and optical masks.
• Photolithography steps are:
• Photoresist Coating
• Exposure
• Development/Etching
• Hard bake

Lithography Process
• Will understand it first as it is going to be repeated
many places….

Spinning of Photoresist Coating
• Photoresist coating : A light-sensitive polymer
(latex) is evenly spread (thickness 1 mm) by spinning
the wafer.

Type of Photoresist
• Negative photoresist:
• Originally soluble in organic solvent
• light exposure causes cross-linking making exposed
regions insoluble.

Types of Photoresist
• Positive photoresist:
• Originally insoluble
• exposure makes it soluble.
• Positive photoresist has higher resolution compared
to negative resolution

Lithography @ smaller geometry
• Feature size reduction puts an enormous burden on
semiconductor equipment manufacturers, particular
those involved with optolithography.
• The dimensions of features transcribed are smaller
than the wavelengths of the optical light sources. Most
photolithography is done using UV with 248nm
wavelength BUT… current geometries << 248nm =>
interference problems

Lithography for Smaller Geometry
• Optical mask correction (OPC) warps the
mask's patterns to allow feature sizes down to
~100 nm to overcome the diffraction
phenomena.
• Phase shift masks (PSM) vary the thickness of
the mask to create interference patterns.
• These and other techniques increase resolution
to 1/8 of the wavelength.
• Sources are lasers at 248 nm and 193 nm
(future 157 nm and 13.4nm)
• Extreme ultraviolet, X ray and electron beam
are potential replacements.

Types of Lithography
A. Optical/UV/EUV
Photolithography
B. E-beam/Ion
Beam/Atomic beam
lithography
C. X-Ray lithography
D. Interference
Lithography
E. Scanning
Probe

Etching

Wet etching
• Material is selectively
removed from areas
that are not covered
by photoresist using
acids, bases and
caustic solutions.
• Chemicals used here
can be very
dangerous to
humans and the
environment.
• Hydrofluoric acid
(HF) is used for SiO2.
Dry etching or
plasma etching
• popular.
• Wafer is given a negative
charge in a chamber heated to
100 degrees C under vacuum.
• A positively charged plasma is
introduced (usually a mix of
nitrogen, chlorine and boron
trichloride).
• Rapidly moving plasma causes
a chemical sandblasting
action in the well defined
direction of the electric field.
• Clean vertical cuts

Highly Anisotropic Etching is required

Hole Profile
( Design For Manufacturing!!!)

Methods of Inserting Impurity Atoms into
Si Substrate
• Diffusion
• impurity applied at Si surface, high
temperature and long time, control of doping
concentration not very precise
• Ion implantation
• impurity applied by scanning a high energy
focussed ion beam at Si surface, low
temperature, acceleration, precise control of
doping concentration

Doping Profile

Limitations of Diffusion
• Diffusion is a relatively less expensive process.
• However, the depth of doping and the quantity of
doping is not precisely controllable.
• When the transistor dimensions were 10 micron
(i.e.10,000 nm)or so, if the variability in doping level is
100 nm, it was acceptable because it was only 1%.
• When the transistor size itself is 100 nm, this much
variability is not acceptable.

Ion Implantation
• When transistor size is 100nm or small, ion
implantation is used.
• In ion implantation, the phosphorous (or boron) must
be first ionized. Then they must be accelerated and
made to impinge on the wafers. Then they will
penetrate into the wafer.
• Similar to firing bullets into a solid wooden door. The
bullets will get embedded into the wood.

Schematic of Ion Implantation
• For doping Boron : boron trifluoride (BF3)
• For doping Phosphorus: phosphorous pentoxide
(P2O5)

Ionizing Chamber

Selection Chamber

Ion Accelerator

Doping Chamber

Comparison of Ion Implant with diffusion
• The deposition plus diffusion process depends on the
chemical nature of the species and the solubility. We can
never implant more than the solubility limit of the dopant
by the diffusion process while in ion implantation, more
than solubility limits can be doped.
• We can control the junction depth, and profile much
better than implantation
• we can also see or ensure that the maximum
concentration of the dopant occurs inside in a specific
location whereas in diffusion, the maximum
concentration will always occur on the surface
• In the diffusion, the side diffusion is significant in ion
implantation even though there is transverse struggle –
the movement to the side is relatively less

Physical Vapour Deposition for Thin Film
• Physical Vapour Deposition is characterized by a
process in which the material goes from a condensed
phase to a vapor phase and then back to a thin film
condensed phase

Chemical Vapor Deposition for Thin Film
• Chemical vapor deposition (CVD) is
a deposition method used to produce high quality,
high-performance, solid materials, typically under
vacuum. The process is often used in the
semiconductor industry to produce thin films.

n-well CMOS Inverter

Simplified CMOS Fabrication Steps
1. Create Field Oxide
2. Create n-well region
3. Grow field oxide and gate oxide
4. Deposit and pattern polysilicon layes
5. Implant source, drain and substrate contact region
6. Create contact window and deposit and pattern
metal layer

Oxide: an essential Component
1. As Gate: It is called gate oxide, an essential part of
the structure
2. As protecting layer of the silicon surface:
Passivation layer.
3. As good insulator : between the wires and
between the transistors
4. In some processes it is used as a sacrificial layer.

Device Isolation
• The MOS transistors must be electrically isolated
• to prevent unwanted conduction path between devices
• to avoid creation of inversion layers outside the
channel regions
• to reduce leakage current
• Thermal grown oxide is mainly used as isolation of
neighbouring transistors
Isolation Techniques
• Junction Isolation
• Etched Field Oxide Isolation
• Local Oxidation of Silicon (LOCOS)
• Shallow Trench Isolation

Junction Isolation

Etched Field Oxide Isolation
• A thick layer of oxide is created on substrate.
• SiO2 growth consumes silicon, grows into the
substrate.
• SiO2 is twice the volume of Si, projects above the
substrate as well.
• The thick oxide is selectively etched away from the
areas where the transistors are to be grown.

Etched Field Oxide Isolation…
Thin Oxide Growth
• After thick oxide growth for isolation between
transistors, the thin oxide of high quality is grown
covering the surface area of transistor.
• This thin oxide layer will eventually form the gate oxide
of the MoS transistor

Limitations of Etched Field Oxide
Isolation
• Large oxide steps at the boundaries between active
areas and isolation region
• When polysilicon and metal layers are deposited over
such boundaries in subsequent steps the sheer height
differences can cause cracking of deposited layers.
• This leads to chip failure

LOCOS
1. a very thin silicon oxide layer known as pad oxide is
grown on the wafer
2. a layer of silicon nitride is deposited which is used
as an oxide barrier
3. The pattern transfer is performed by
photolithography
4. After lithography the pattern is etched into the
nitride
5. the growth of the thermal oxide
6. the removal of the nitride layer

Local Oxidation of Silicon (LOCOS)

LOCOS
Advantage:
• Simple process flow
• High oxide quality
Disadvantage:
• Bird’s beak effect: loss of surface area due to this
encroachment

Shallow Trench Isolation (STI)
• Completely avoid bird’s beak
• Preferred at submicron 0.5um technology
Differences:
1. shallow trench is etched into the silicon
substrate
2. a thermal oxide in the trench is grown, the so-
called liner oxide
3. after the formation of a thin oxide layer, and the
rest of the trench is filled with a deposited oxide
4. the excessive (deposited) oxide is removed with
chemical mechanical planarization

Shallow Trench Isolation (STI)
• Bird’s beak is avoided and hence zero encroachment of
oxide field

Parasitic MOS
• If poly or metal line lies on top of FOX (Field Oxide),
they may form a parasitic MOS structure. If this
line carries a high voltage, it may create an
inversion layer below FOX and may short the
neighbouring devices.
• Relatively highly doped Si underneath raises the
threshold voltage of this parasitic MOS.
• If this threshold voltage is higher than the highest
circuit voltage, inversion will never occur.

Channel Stop Implant
• Self aligned
channel stop
implant:
• B+ doping in area
of FOX before the
thermal oxidation
for FOX growth

Creation of n-Well
• By using ion implantation or diffusion process N-well is
formed.

Non-Self Aligned Gate
1. Forming Source and Drain first
2. Forming gate insulator
3. Finally gate is placed on the structure
Disadvantages:
1. Gate length three times larger than the space
between S &D
Extra overlap area between G&S , G&D
hence large stray capacitance
Slow device
2. Defects due to random misalignments
3. Two lithography steps

Non-self aligned Gate

Self Aligned Gate
1. Form the gate insulator first
2. Form a gate od the precise size as desired
spacing between S and D
3. Gate itself is used as mask that established
the source and drain.
4. Source and Drain are precisely aligned with
gate and the space is exactly as required by
gate to cover the channel region.
Advantages:
1. Precise gate length, channel length and
space between S &D
2. Faster as gate length is three times less
3. One lithography step is avoided

Self Aligned Gate
• The gate mask works also as a mask for n+/p+
diffusion mask, there’s no need for separate gate
mask and diffusion masks

Self Aligned Gate
• gate electrode region of a MOSFET transistor is
used as a mask for the doping of the source and
drain regions. This technique ensures that the gate
will slightly overlap the edges of the source and
drain.
• Except the two small regions required for forming
the Gates of NMOS and PMOS, the remaining layer
is stripped off.

Masking and N-Diffusion
• By using the masking process small gaps are made
for the purpose of N-diffusion.
• The n-type (n+) dopants are diffused or ion
implanted, and the three n+ are formed for the
formation of the terminals of NMOS.

P-Diffusion
• The remaining oxidation layer is stripped off.
• Similar to the above N-diffusion process, the P-
diffusion regions are diffused to form the terminals of
the PMOS.

Substrate and well tap
• To connect p-substrate to ground voltage and n well
to VDD voltage, an ohmic contact is required.
• Ohmic contact means transferring the voltage
applied to metal directly to semiconductor without
much loss of voltage.
• p+ is used for substrate tap and n+ is used for well
tap.

Lightly Doped Drain (LDD)
• The n-pockets (LDD) doped to medium concentration
(1E18) are used to smear out the strong electric field
between the channel and heavily doped n+ drain in
order to reduce the hot carrier generation.

Process Steps for S, D and LDD
1. n implant for LDD
2. CVD Conformal deposition of SiO2

LDD
• Removal of SiO2. Spacer left when CVD SiO2 is just
cleared on flat surface
• Spacer will stop further implant

Threshold Adjust
• In n-well, the pMOS is degraded.
• For a perfect CMOS inverter, the threshold of nMOS
and pMOS should match
• Vt of pMOS and nMOS can be adjusted by changing
the doping concentration at channel by applying ion
implantation dose.
• nMOS transistor implanted with n-type dopant results
in decreases in threshold voltage
• nMOS transistor implanted with p-type dopant results
in increase in threshold voltage.

Threshold Adjustment

• A thick-field oxide is formed in all regions except the
terminals of the PMOS and NMOS.

Contacts and Terminals

Metallization
• Typically 4-8 metal layers for power supply, ground,
signals and interconnect between transistors
• Each layer must be electrically isolated by SiO2
• Electrical connections between layers by Vias
• Each via by creating an window in isolation layer and
filling it with a special metal plug of tungsten
• After that layer of metal
• Patterning of metal layer

Planarization
• The surface becomes non-planer because of various
steps for transistor fabrication
• It is not desirable to deposit multiple metal layers on
uneven surface as it may create localized thinning and
discontinuities
• Chemical-Mechanical Planarization (CMP) is
performed before each metal deposition layer to reduce
the step heights in the SiO2.
• The process involves the use of a slurry compound, a
liquid carrier with suspended abrasive components,
e.g., aluminum oxide or silica.

Typical n well CMOS Process

CMOS Inverter Layout in n well CMOS
process

CMOS Inverter in Twin Well CMOS
Process

Twin Tub Process

Current Trends in Fabrication
• Copper Interconnect
• Low-k dielectric for interconnect
• High-k dielectric for transistor gates
• Optical problems (and attempted fixes)

Copper interconnect
• Copper is a much better conductor than aluminum
• But, it tends to chemically react with silicon
dioxide
• Fabrication of copper wires: “damascene” process
• Etch trenches in the surface where wires will be placed
• Coat with “secret chemical” (isolates Cu, silicon, oxide)
• Coat with layer of copper
• Polish wafer to remove copper except in trenches

Alternative Dielectrics
• Dielectric constant of SiO2: 3.9
• Problem: want to minimize coupling capacitance
between wires
• Solution: “low-k” dielectrics (featured in 130nm and
below)
• Proposed materials would have approx K=3
• Problem: want to maximize electric field under
transistor gates
• Solution: “high-k” dielectrics (anticipated in 90nm and
below)
• Proposed materials would have K>>4

Wire Bonding

Thanks!

IC Fabrication Process Overview

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to IC Fabrication Process Overview

Similar to IC Fabrication Process Overview (20)

More from Usha Mehta

More from Usha Mehta (16)

Recently uploaded

Recently uploaded (20)

IC Fabrication Process Overview