Testing and Verification of VLSi Design

1. Set-up and Hold Time
Violation
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org

2. 1/25/2022
Static
Timing
Analysis
Considering the delays….
1. Ideal Condition no delay in any path.
2. Data and Clock path have fixed delays but
no set-up/Hold time for FFs
3. Data and Clock path have fixed delays and
FFs are with set-up/Hold time
4. Data and Clock path have delays, FFs are
with set-up/Hold time ( all delays with min-
max range, not fixed)
2

3. 1/25/2022
Static
Timing
Analysis
Ideal Condition: No delays
3

4. 1/25/2022
Static
Timing
Analysis
Launching, arrival and capture
moments
4

5. 1/25/2022
Static
Timing
Analysis
Delays in Data and Clock Path
5

6. 1/25/2022
Static
Timing
Analysis
Delays in Data Path and Clock Path
contd…
6

7. 1/25/2022
Static
Timing
Analysis
Conditions for
Timings
7

8. 1/25/2022
Static
Timing
Analysis
Set up Time and Hold Time
• Set up Time
• For an edge triggered sequential element, the setup time is
the time interval before the active clock edge during which
the data should remain unchanged.
• This is so that the data can be stored successfully in storage
device
• Because of Long path
• Hold Time
• Time interval after the active clock edge during which the
data should remain unchanged. This is so that the data can
be stored successfully in storage device
• Because of Short Path
8

9. 1/25/2022
Static
Timing
Analysis
Setup Time and Hold Time Consideration
9

10. 1/25/2022
Static
Timing
Analysis
Setup and Hold
Time consideration
contd….
10

11. 1/25/2022
Static
Timing
Analysis
When delays are given in min-max
limits
11

12. 1/25/2022
Static
Timing
Analysis
Set-up Time Violation
12

13. 1/25/2022
Static
Timing
Analysis
Hold Time Violation
13

14. 1/25/2022
Static
Timing
Analysis
Relation between data path delay, clock
path delay, Set-up/Hold and Clock Time
Period…
1. The circuit is given with all delays ( net,
cell, Set-up, hold etc..)
• you are required to calculate the
minimum time period (maximum
frequency) of clock.
2. The circuit is given with all delays ( net,
cell, Set-up, hold etc..) and minimum time
period (maximum frequency) of clock at
which circuit will operate.
• You are required to verify whether any timing
violation exists or not.
14

15. 1/25/2022
Static
Timing
Analysis
Calculate the max. clock frequency
for given circuit…
• Minimum Time Period = tclk-q + tpd + ts = 10 + 5 +2 =
17ns
15

16. 1/25/2022
Static
Timing
Analysis
16
TAB = 11ns, TAC = 15ns , TBC = 16ns.
Minimum clock period =16ns
Calculate the max. clock frequency
for given circuit…

17. 1/25/2022
Static
Timing
Analysis
17
Tclk-Q = 10 ns, NOR/OR = 4 ns, NAND/AND =3 ns,
INV/BUF = 2ns, Ts = 2 ns, Th = 3ns
Calculate the max. clock frequency
for given circuit…

18. 1/25/2022
Static
Timing
Analysis
18
For a minimum clock period, we just want that the data reach ts time
before the clock reach there.
Data path
• Max delay = 26ns
• Min delay = 18ns
Clock Path
• Max delay = 15ns
• Min delay=9ns
Minimum Clock Period = 26 -9 +4 = 21 ns
Calculate the max. clock frequency
for given circuit…

19. 1/25/2022
Static
Timing
Analysis
Find out any set-up violation ?
• For set-up path
• Set-up is checked at next clock cycle
• Maximum delay along the data path
• Minimum delay along the clock path
• Data path is
• CLK->FF1/CLK->FF1/Q->INV->FF2/D
• TD =2ns +11ns+2ns+9ns+2ns = 26ns ( max. delay in data path)
• Clock Path is
• CLK-> BUFF->FF2/CLK
• TCLK= 15 ns + 2ns+5ns+2ns-4ns = 20ns (max. delay in clock
path)
• SET-UP SLACK = TCLK-TD
• 20-26= -6ns < 0 so Set-Up Violation
19
CLK Period = 15ns

20. 1/25/2022
Static
Timing
Analysis
Find out any hold violation?
• For hold path
• Hold is checked at Same clock cycle
• Minimum delay along the data path
• Maximum delay along the clock path
• Data path is
• CLK->FF1/CLK->FF1/Q->INV->FF2/D
• TD =1ns +9ns+1ns+6ns+1ns = 18ns ( min. delay in data path)
• Clock Path is
• CLK-> BUFF->FF2/CLK
• TCLK= 3ns+9ns+3ns+2ns = 17ns (max. delay in clock path)
• SLACK = TD-TCLK
• 18-17=1ns > 0 so No Hold Violation 20

21. 1/25/2022
Static
Timing
Analysis
Fixing Set-up /Hold Violation
:Combinational Delay
• Check for violations
• Data1 reaches to FF2 at 0.5 ns. It should reach before 10 ns – 2ns i.e
8ns Hence, NO set-up violation
• Data2 launched at 10 ns, reaches to FF2 at 10.5 ns. It disturbs the
data1 which should be there upto 11ns. So hold violation.
• To remove hold violation, let’s increase the combinational delay.
Let’s say by 3ns. Then data1 reaches at 3ns which is before 8ns so
still no problem with set-up time and data2 reaches at 13ns so hold
time violation is also solved.
• But what if we increase combination delay to 9ns? Here, while
solving for hold-time, we have violated setup time.
21

22. 1/25/2022
Static
Timing
Analysis
22
Fixing Set-up /Hold Violation
• Check for violations

23. 1/25/2022
Static
Timing
Analysis
Timing Closure
• It is the process of satisfying timing constraints
through layout optimizations and netlist
modifications
• Timing-driven placement: minimizes signal
delays when assigning locations to circuit
elements
• Timing-driven routing : minimizes signal delays
when selecting routing topologies and specific
routes
• Physical synthesis: improves timing by
changing the netlist
• Sizing transistors or gates: increasing the width:length ratio of
transistors to decrease the delay or increase the drive strength
of a gate
• Inserting buffers into nets to decrease propagation delays
• Restructuring the circuit along its critical paths
23

24. 1/25/2022
Static
Timing
Analysis
Ways to fix set-up Violation
(Tdata <= Tclk-Tsetup)
1. Reduce the amount of buffering in the path.
 It will reduce the cell delay but increase the wire delay. So if effective
delay is reduced than, set-up time violation can be fixed.
2. Replace buffer with two inverters place farther apart
 Delay of one buffer is equal to delay of two inverter but because of two
inverters, the transition delays are reduced.
3. Change HVT cells to SVT/LVT to reduce delay
 HVT/SVT/LVT has the same size and pin position so this change will
reduce delay without affecting layout.
4. Increase driver size i.e. driver strength
 It reduces delay
5. Insert Buffer/repeaters
 In case of long wire, the buffer decreases the transition time which
decreases wire delay. If decrease in wire delay is more compared to buffer
delay, overall delay reduces.
24

25. 1/25/2022
Static
Timing
Analysis
Ways to fix set-up Violation
(Tdata <= Tclk-Tsetup) cont…..
6. Adjust Cell position in layout
7. Clock Skew
 By delaying clock to the end point.
25

26. 1/25/2022
Static
Timing
Analysis
Ways to fix hold time violation…
Tdata >= Thold
1. By adding delay
 The hold violation path may have its start or stop point in
other setup violation path
2. Decreasing the size of cells in data path
26

27. 1/25/2022
Static
Timing
Analysis
Negative Set-up and Hold Time
• For a Pure flop(containing no extra gates) setup
and hold time always will be a positive number.
• Now, A flop can be a part of a bigger
component. There are many components
available in stranded cell library that embed a
flop inside. These components will be a part of
our design.
• Setup and hold time can be negative depending
on where you measure the setup and hold time,
if you measure setup and hold time at
component level. These can be negative also.
27

28. 1/25/2022
Static
Timing
Analysis
Negative Set-up and Hold Time
• For pure flipflop
• Tdata < Tclk-Tsetup
• Tdata > Thold
28
Flipflop
(Pure)
Tdata
Tclk
Tsetup Thold

29. 1/25/2022
Static
Timing
Analysis
Negative Set-up and Hold Time
29
Flipflop
(Embedded)
Tdata
Tclk_comp
Tsetup
Thold
Tdata_delay
Tclk_delay
Tcomp_setup Tcomp_hold

30. 1/25/2022
Static
Timing
Analysis
Negative Set-Up Time
• The time when data reaches to flipflop = Tdataflipflop = Tdata+Tdata_delay
• The time when clock reaches to flipflop = Tclkflipflop = Tclk_comp+Tclk_delay
• Considering flipflop, Tdata+Tdata_delay < Tclk_comp+Tclock_delay-Tsetup
• If Tdata_delay= 700, Tclk_delay = 800 and Tsetup=200
• Tdata+700 <= Tclk_comp + 800-200
• Tdata <= Tclk_comp-100
• Tcomp_setup is 100
• But If Tdata_delay= 500, Tclk_delay = 800 and Tffsetup=200
• Tdata+500 <= Tclk_comp+800-200
• Tdata <= Tclk_comp + 100
• Tcomp_setup is negative i.e. -100
30
For Component, Tdata < Tclk_comp-Tcomp_setup

31. 1/25/2022
Static
Timing
Analysis
Negative Hold Time
• The time when data reaches to flipflop = Tdataflipflop = Tdata+Tdata_delay
• The time when clock reaches to flipflop = Tclkflipflop = Tclk_comp+Tclk_delay
• Tdata+Tdata_delay >= Thold
• If Tdata_delay= 100, and Thold=200
• Tdata+100 >= 200
• Tdata >= 100
• Tcomp_hold is 100
• If Tdata_delay= 300 and Thold=200
• Tdata+300 >= 200
• Tdata >= -100
• Tcomp_hold is negative i.e. -100
31
For Component Tdata > Tcomp_hold

32. 1/25/2022
Static
Timing
Analysis
Time Borrowing/ Cycle Stealing
• Technique of borrowing the time from shorter
path of the logic stage to the longer path
• Do remember:
• Edge triggered flipflop changes the stage at the clock edges So
the delay of a combination logic path in a design using such FFs
can not be longer than the clock period of the design ( except for
false or multicycle path)
• While the latch can change the stage as long as clock pin is
enabled. Here, the delay of the longest path can be compensated
by the delay of the shortest path in subsequent logic design
• Hence latch based design can be faster.
32

33. 1/25/2022
Static
Timing
Analysis
Example of Time Borrowing
33

34. 1/25/2022
Static
Timing
Analysis
STA in ASIC Design Flow – Pre layout
34
Logic Synthesis
Design For test
Floor planning
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
Static Timing Analysis
(estimated parasitics)

35. 1/25/2022
Static
Timing
Analysis
STA in ASIC Design Flow – Post Layout
35
Floor planning
Clock Tree Synthesis
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
(estimated parasitics)
Static Timing Analysis
(extracted parasitics)

36. 1/25/2022
Static
Timing
Analysis
Required Inputs
36

37. 1/25/2022
Static
Timing
Analysis
Back Annotation – A process
1. Designer writes the RTL and performs functional simulation
considering delay as zero or some unit value as in simulator’s
library file.
2. The RTL description is converted to gate level netlist by a logic
synthesis tool.
3. The designer estimates the prelayout estimates of delays in the chip
using a delay calculator and information about the IC fabrication
process (.sdf)
4. The designer does timing simulation or static timing verification of
the gate level netlist using this preliminary values to check that the
gate level netlist meets timing constraint
5. The gate level netlist is then converted into layout by place and
route tool
6. The postlayout delays are now calculated from the R and C
information in the layout. This R and C depends on technology and
geometry of IC
7. The post layout delay values are back annotated to modify the delay
estimates of the gate level netlist
8. Again timing simulation or STA to check the timings are still
satisfied.
9. If needed, design changes 37

38. 1/25/2022
Static
Timing
Analysis
Back Annotation
38

39. 1/25/2022
Static
Timing
Analysis
Standard Delay Format
• IEEE standard for the representation and interpretation of
timing data for use at any stage of an electronic design
process.
• It has usually two sections: one for interconnect delays and
the other for cell delays.
• SDF format can be used for back-annotation as well as
forward-annotation.
39

40. Thanks!
40