- 1. ATPG System Dr Usha Mehta usha.mehta@ieee.org usha.mehta@nirmauni.ac.in
- 2. Acknowledge • This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t itemwise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 DrUshaMehta03-12-2019
- 3. Introduction • Test generation is the bread-and-butter in VLSI Testing • Efficient and powerful ATPG can alleviate high costs of DFT • Goal: generation of a small set of effective vectors at a low computational cost • ATPG is a very challenging task • Exponential complexity • Circuit sizes continue to increase (Moore’s Law) • Aggravate the complexity problem further • Higher clock frequencies • Need to test for both structural and delay defects 3 DrUshaMehta03-12-2019
- 4. Methods for Test Pattern Generation • Exhaustive • Pseudo-Exhaustive • Random • Pseudo-random • Weighted Random • Deterministic 4 DrUshaMehta03-12-2019
- 5. Exhaustive Test Pattern Generation • Exhaustive -- all possible input test patterns • Example: 2n patterns for input combinational logic circuit with n inputs • Guarantees all detectable faults in the combinational circuits are detected • Test time maybe be prohibitively long if the number of inputs is large • Feasible only for small circuits. Infeasible unless circuit is partitioned into various cones with inputs < 15 • Pseudo Exhaustive • Partition the circuit into cones • each partitioned sub--circuit is exhaustively tested • Misses faults that requires specific activation patterns for multiple cones to be tested. 5 DrUshaMehta03-12-2019
- 6. Random Test Pattern generation • Random -- true random patterns • Select any pattern randomly and see how many faults it detects. • Fault simulation is necessary in order to decide which faults are being detected by that pattern. • Level of confidence on random test set T • The probability that T can detect all stuck-at faults in the given circuit • Quality of a random test set highly depends on the underlying circuit • Some circuits have many random-resistant faults • Pseudo--random - properties similar to random sequences but repeatable 6 DrUshaMehta03-12-2019
- 7. Weighted Pseudo Random Test Pattern Generation • Specific bits produce more 1s or 0s • Bias input probabilities to target random resistant faults • Consider an 8-input AND gate • Without biasing input probabilities, the prob of generating a logic 1 at the gate output = (0.5)8 = 0.004 • If we bias the inputs to 0.75, then the prob of generating a logic 1 at the gate output = (0.75)8 = 0.100 • Obtaining an optimal set of input probabilities a difficult task • Goal: increase the signal probabilities of hard-to-test regions 7 DrUshaMehta03-12-2019
- 9. Deterministic Test Patterns Generation using Boolean Difference • Given a circuit with output f and fault • The set of vectors that can detect this fault includes all vectors that satisfy • Do we really need all test vectors to detect a fault? 9 DrUshaMehta03-12-2019
- 10. Deterministic Test Pattern Generation using Algorithms • In general, we don’t need an entire set of vectors that can detect the target fault • Instead, we just want to compute one vector quickly • Rather than using Boolean Difference that can obtain all vectors • Simply use a branch-and-bound search to find one vector quickly • Deterministic ATPG has two main goals • Excite the target fault • Propagate the corresponding fault effect to an output 10 DrUshaMehta03-12-2019
- 12. Automatic Test Pattern Generator • Reduce cost of test generation (development) • Two phase approach to test generation • Phase 1: low cost methods initially • Many faults can be detected with little effort. • Use random vectors and fault simulation. • Initially the coverage rises rather fast. • Like a soldier with machinegun kills enemy randomly and fast • Phase 2: use methods that target specific faults till desired fault coverage is reached • Automatic Test Pattern Generation for targeted faults • Soldier with pistol shoots the remaining enemies with proper direction. 12 DrUshaMehta Testing@VGEC 03-12-2019
- 13. How to decide the test set? • Fault Simulation • For given test vector, prepare the list of faults being detected by that test vector • Deterministic Test Pattern Generation • For given fault, prepare the list of test vectors that detects the given fault. • Which to choose? 13 DrUshaMehta03-12-2019
- 14. Which to choose? Fault simulation or ATPG? • Reduce cost of test generation (development) • Two phase approach to test generation • Phase 1: low cost methods initially • Many faults can be detected with little effort. • Use random vectors and fault simulation. • Initially the coverage rises rather fast. • Like a soldier with machinegun kills enemy randomly and fast • Phase 2: use methods that target specific faults till desired fault coverage is reached • Automatic Test Pattern Generation for targeted faults • Soldier with pistol shoots the remaining enemies with proper direction. 14 DrUshaMehta03-12-2019
- 15. When to switch over from Phase-I to Phase-II • Phase-I : Random Pattern Generation & Fault Simulation • When to stop phase-I • Continue as long as many faults are detected by next coming test vector • Discard the test vector that does not detect many new faults • When many such vectors are discarded consecutively, stop phase-I and switch over to phase-II 15 DrUshaMehta03-12-2019
- 16. When to stop Phase-II? • Phase-II: List the targeted fault, Automatic Test Pattern Generator • When to stop Phase-II • User constrained limits for • Backtracking • Selection of next fault • Declaration of fault as undetectable 16 DrUshaMehta03-12-2019
- 19. Quality Parameters of ATPG System • Efficient heuristics for backtrace • What fault to pick next • Choice of backtrack limit • Switch heuristics • Interleave test generation and fault simulation • Fill in x’s (test compaction) • Identify untestable faults by other methods 19 DrUshaMehta03-12-2019