3 test economic_test_equipments_yield
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This document discusses test equipment and test economics in three areas: 1. It describes the basic components and functions of automatic test equipment (ATE), including powerful computers, digital signal processors, test programs, probe heads, and probe cards for performing tests on chips. 2. It explains different types of tests including parametric tests that measure electrical properties and functional tests that test all transistors and wires. Test planning involves specifying requirements, selecting test equipment, and determining fault coverage. 3. It discusses the economics of testing including costs of different test strategies, benefit-cost analysis of design-for-testability techniques, and how yield and defect levels relate to test quality and costs. Overall economics aims to maximize quality while minimizing
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3 test economic_test_equipments_yield
- 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Dr Usha Mehta 25-01-2022
- 4. Motivation • Need to understand Automatic Test Equipment (ATE) technology • Influences what tests are possible • Serious analog measurement limitations at high digital frequency or in the analog domain • Understand capabilities for digital logic, memory, and analog test for testing System-on-a-Chip (SOC) • Need to understand parametric testing • For setup and hold time measurements • For determination of VIL , VIH , VOL , VOH , tr , tf , td , IOL, IOH , IIL, IIH 4 1/25/2022
- 5. Automatic Test Equipment (ATE) • Consists of: • Powerful computer • Powerful 32-bit Digital Signal Processor (DSP) for analog testing • Test Program (written in high-level language) running on the computer • Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) • Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad) 5 1/25/2022
- 6. Types of Tests • Parametric • measures electrical properties of pin electronics • delay, voltages, currents, etc. • fast and cheap • Functional • used to cover very high % of modeled faults – test every transistor and wire in digital circuits • long and expensive 6 1/25/2022
- 7. Test Specifications & Plan • Test Specifications: • Functional Characteristics • Type of Device Under Test (DUT) • Physical Constraints – package, pin numbers, etc. • Environmental Characteristics – power supply, temperature, humidity, etc. • Reliability – acceptance quality level (defects/million), failure rate, etc. • Test plan generated from specifications • Type of test equipment to use • Types of tests • Fault coverage requirement 7 1/25/2022
- 9. Test Data Analysis • Uses of ATE test data: • Reject bad DUTs • Fabrication process information • Design weakness information • Devices that did not fail are good only if tests covered 100% of faults • Failure mode analysis (FMA): • Diagnose reasons for device failure, and find design and process weaknesses • Improve logic and layout design rules 9 1/25/2022
- 12. T6682 ATE Block Diagram 12 1/25/2022 Algorithmic Pattern Generator Scan Pattern Generator Sequential Pattern Generator Pin Electronic Parametric Measuremen
- 13. T6682 ATE Specifications • Uses 0.35μ VLSI chips in implementation • 1,024 digital pin channels • Speed: 250, 500, or 1000 MHz • Timing accuracy: +/- 200 ps • Drive voltage: - 2.5 to 6 V • Clock/strobe accuracy: +/- 870 ps • Clock settling resolution: 31.25 ps • Pattern multiplexing: write 2 patterns in one ATE cycle • Pin multiplexing: use 2 pins to control 1 DUT pin 13 1/25/2022
- 14. Pattern Generation • Sequential pattern generator (SQPG): stores 16 Mvectors of patterns to apply to DUT -- vector width determined by # DUT pins • Algorithmic pattern generator (ALPG): 32 independent address bits, 36 data bits • For memory test – has address descrambler • Has address failure memory • Scan pattern generator (SCPG) supports JTAG boundary scan, greatly reduces test vector memory for full-scan testing • 2 Gvector or 8 Gvector sizes 14 1/25/2022
- 15. Response Checking and Frame Processor • Response Checking: • Pulse train matching – ATE matches patterns on 1 pin for up to 16 cycles • Pattern matching mode – matches pattern on a number of pins in 1 cycle • Determines whether DUT output is correct, changes patterns in real time • Frame Processor – combines DUT input stimulus from pattern generators with DUT output waveform comparison • Strobe time – interval after pattern application when outputs sampled 15 1/25/2022
- 16. Probing • Pin electronics (PE) – electrical buffering circuits, put as close as possible to DUT • Uses pin connector at test head • Test head interface through custom printed circuit board to wafer prober (unpackaged chip test) or package handler (packaged chip test), touches chips through a socket (contactor) • Uses liquid cooling • Can independently set VIH , VIL , VOH , VOL, IH , IL, VT for each pin • Parametric Measurement Unit (PMU) 16 1/25/2022
- 17. Probe Card and Probe Needles or Membrane • Probe card – custom printed circuit board (PCB) on which DUT is mounted in socket – may contain custom measurement hardware (current test) • Probe needles – come down and scratch the pads to stimulate/read pins • Membrane probe – for unpackaged wafers – contacts printed on flexible membrane, pulled down onto wafer with compressed air to get wiping action 17 1/25/2022
- 18. T6682 ATE Software • Runs Solaris UNIX on UltraSPARC 167 MHz CPU for non-real time functions • Runs real-time OS on UltraSPARC 200 MHz CPU for tester control • Peripherals: disk, CD-ROM, micro-floppy, monitor, keyboard, HP GPIB, Ethernet • Viewpoint software provided to debug, evaluate, and analyze VLSI chips 18 1/25/2022
- 19. LTX FUSION HF ATE 19 1/25/2022
- 21. The Meaning of Economics 21 1/25/2022 Economics is the study of how men choose to use scarce or limited productive resources (land, labor, capital goods such as machinery, and technical knowledge) to produce various commodities (such as wheat, overcoats, roads, concerts, and yachts) and to distribute them to various members of society for their consumption. -- Paul Samuelson The first American to win the Nobel Memorial Prize in
- 22. Engineering Economics 22 1/25/2022 Engineering Economics is the study of how engineers choose to optimize their designs and construction methods to produce objects and systems that will optimize their efficiency and hence the satisfaction of their clients.
- 23. Costs • Fixed cost • Variable cost • Total cost • Average cost 23 1/25/2022 Example: Costs of running a car Fixed cost Variable cost Total cost Average cost $25,000 20 cents/mile $25,000 + 0.2x $ ───── + 0.2 25,000 x Purchase price of car Gasoline, maintenance, repairs For traveling x miles Total cost / x
- 24. Simple Cost Analysis 24 1/25/2022 Case 1: 10,000 miles/yr, $12,500 resale value after 5 years Average cost = $ ────────── + 0.2 = 45 cents/mile 25,000 - 12,500 50,000 Case 2: 10,000 miles/yr, $6,250 resale value after 10 years Average cost = $ ───────── + 0.2 = 38.75 cents/mile Case 3: 10,000 miles/yr, $0 resale value after 20 years Average cost = $ ─────── + 0.2 = 32.5 cents/mile 25,000 - 6,250 100,000 25,000 - 0 200,000
- 25. Cost Analysis Graph 25 1/25/2022 40,000 25,000 20,000 200k 150k 100k 50k 100 50 0 0 0 Miles Driven Fixed, Total and Variable Costs ($) Average Cost (cents) Fixed cost Average cost
- 26. Benefit-Cost Analysis • Benefits: Savings in manufacturing costs (capital and operational) and time, reduced wastage, automation, etc. • Costs: Extra hardware, training of personnel, etc. • Benefit/cost ratio 26 1/25/2022 Annual benefits B/C ratio = ───────────── > 1 Annual costs
- 27. Example: A PCB Repair Shop • Average cost of repair = $350, includes • Cost of diagnostic test = $300 • Cost of replacement any one chip = $ 10 • Cost of assembly and test = $ 40 27 1/25/2022 Faulty PCB Apply diagnostic Test Cost = $300 Replace faulty Chip and test Cost = $50 Repair completed Av. Cost = $350
- 28. Example: A PCB Repair Shop • Average cost of repair = $350, includes • Cost of diagnostic test = $300 • Cost of replacement any one chip = $ 10 • Cost of assembly and test = $ 40 • Failure data Analysis for 100 chips on PCB shows that • Chip A failure rate = 90% • Chip B failure rate = 90% • Collective failure rate for chips A and B = 0.9 + 0.9 – 0.81 = 0.99 • What strategy should be adopted after Failure data analysis? 28 1/25/2022
- 29. PCB Repair Strategies 29 1/25/2022 Faulty PCB Replace chips A and B and test Cost = $60 Replace faulty Chip and test Cost = $50 PCB passes Test? Apply diagnostic Test Cost = $300 Repair completed Av. Cost = $63.50 Yes Prob=0.99 No Prob=0.01 Strategy 2
- 30. Economics of Design for Testability (DFT) • Consider life-cycle cost; DFT on chip may impact the costs at board and system levels. • Weigh costs against benefits • Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests • Benefit examples: Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test 30 1/25/2022
- 31. Benefits and Costs of DFT 31 1/25/2022 Design and test + / - + / - + / - Fabri- cation + + + Manuf. Test - - - Level Chips Boards System Maintenance test - Diagnosis and repair - - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction
- 32. Summary of Economics • Economics teaches us how to make the right trade-offs. • It combines common sense, experience and mathematical methods. • The overall benefit/cost ratio for design, test and manufacturing should be maximized; one should select the most economic design over the cheapest design. • A DFT or test method should be selected to improve the product quality with minimal increase in cost due to area overhead and yield loss. 32 1/25/2022
- 33. VLSI Chip Yield • A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. • A chip with no manufacturing defect is called a good chip. • Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. • Cost of a chip: 33 1/25/2022 Cost of fabricating and testing a wafer ────────────────────────── Yield × Number of chip sites on the wafer
- 34. Clustered VLSI Defects 34 1/25/2022 Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77
- 35. Defect Level or Reject Ratio • Defect level (DL) is the ratio of faulty chips among the chips that pass tests. • DL is measured as parts per million (ppm). • DL is a measure of the effectiveness of tests. • DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. 35 1/25/2022
- 36. Determination of DL • From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. • From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. 36 1/25/2022
- 37. • Defective Parts Per Million (DPPM):key metrics used to measure quality in many semiconductor segments • For mission-critical segments such as automotive and medical : DPPB (Per Billion) • For a premium vehicle • more than 7,000 semiconductor devices • If you assume a DPPM rate of 1 for all the semiconductor devices • it equates to seven failures for every 1,000 cars 37 1/25/2022
- 38. DPM and Test Coverage • Considering DPM=100 means 100 bad ICs out of 1000,000 are escaping the test • It means in 1000,000, there are 100 bad ICs and 999,900 good Ics • Test Coverage = 999,900/1000,000=99.99% 38 1/25/2022
- 39. Yield and DPM • Assuming 10% yield and manufactured ICs are 1000,000 • 100,000 good IC, 900,000 bad ICs • Considering 99.99% test coverage • It means 0.01% faulty ICs are shipped • It means 90 ICs out of 900,000 bad ICs escaped the test and shipped along 100,000 good ICs. • Now in 100,090 ICs, 90 ICs are defective • Almost 900 DPM 39 1/25/2022
- 40. For Technology with smaller Geometry • For Digital • 100 to 1000 DPM • For Analog and Mission Critical • Zero DPM • For 10nm Technology, 20% yield for many years for Intel 40 1/25/2022
- 41. Summary • VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (α). • Yield drops as chip area increases; low yield means high cost. • Fault coverage measures the test quality. • Defect level (DL) or reject ratio is a measure of chip quality. • DL can be determined by an analysis of test data. • For high quality: DL < 500 ppm, fault coverage ~ 99% 41 1/25/2022