As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
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Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
https://www.udemy.com/vlsi-academy
The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.
Physical verification will verify that the post-layout netlist and the layout are equivalent. i.e. all connections specified in the netlist is present in the layout. This article explains physical verification.
This is the presentation that was shared by Nilesh Ranpura and Vineeth Mathramkote at CDNLIVE 2015. The session briefs about the implementation challenges and covers the solution approach and how to achieve results
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
Note : To get more understanding Recommending to see first section - Low power in vlsi with upf basics part 1
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
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Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
https://www.udemy.com/vlsi-academy
The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.
Physical verification will verify that the post-layout netlist and the layout are equivalent. i.e. all connections specified in the netlist is present in the layout. This article explains physical verification.
This is the presentation that was shared by Nilesh Ranpura and Vineeth Mathramkote at CDNLIVE 2015. The session briefs about the implementation challenges and covers the solution approach and how to achieve results
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
Note : To get more understanding Recommending to see first section - Low power in vlsi with upf basics part 1
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
STUDY OF PROCESS PARAMETER OF WIRE ELECTRIC DISCHARGE MACHINING: THE REVIEWIAEME Publication
Wire EDM is a variation of the Electric Discharge Machining and is commonly known as wire-cut EDM. In WEDM, material is eroded from the work material by a series of discrete sparks
occurring between the work piece and the wire which is generally act as electrode, separated by a stream of dielectric fluid. Dielectric fluid commonly used is deionized water which is act as coolant and flushes the debris away. Work piece is generally electric conductive.
Transients can cause slow degradation, erratic operation, or catastrophic failure in electrical parts, insulation dielectrics, and electrical contacts used in switches and relays. The possible occurrence of transients must be considered in the overall electronic design. Required circuit performance and reliability must be assured both during and after the transient
POWER SYSTEM PROTECTION
Protection Devices and the Lightning,. protection,
Lightning protection, Introduction
Air Break Switches
Disconnect switches
Grounding switches
Current limiting reactors
Grounding transformers
Co-ordination of protective devices
Grounding of electrical installations
Electric shock
Lightning protection
Lightning Arrestor
The term high voltage characterizes electrical circuits in which the voltage used is the cause of particular safety concerns & insulation requirements. High voltage is used in electrical power distribution, in cathode ray tubes, to generate x-rays & particle beams, to demonstrate arcing, for ignition, in photomultiplier tubes & high power amplifier vacuum tubes & other industrial & scientific applications .
Behavioral studies of surge protection componentsjournalBEEI
In our daily life, almost all the items we used, being a computer, television, lift or vehicle we drive consist of some kind of electrical or electronics component inside. The operation of these devices could be severely affected by lightning activity or electrical switching events, as there are more than 2000 thunderstorms in progress at any time resulting in 100 lightning flashes to ground per second. In practice, any device using electricity will subject to surge damages induced from the lightning or switching of heavy load. Surge protection device (SPD) is added at the power distribution panel and critical process loop to prevent damage subsequently cause plant shutdown. There are many questions raised on the SPD. How can this small device protect the equipment from large energy release by the lightning? What is inside the device? How does it work? This paper provides comprehensive detail in revealing the science and engineering behind the SPD, its individual component characteristic and how does it work. The technical information presented is limited to surge protection on equipment; surge protection for building structure will not be discussed here.
Fiction is a form of narrative, one of the four rhetorical modes of discourse. Fiction-writing also has modes for fiction-writing: action, exposition, description, dialogue, summary, and transition (Morrell 2006, p. 127). Author Peter Selgin refers to methods, including action, dialogue, thoughts, summary, scene, and description (Selgin 2007, p. 38). Currently, there is no consensus within the writing community regarding the number and composition of fiction-writing modes and their uses.
Description is the fiction-writing mode for transmitting a mental image of the particulars of a story. Together with dialogue, narration, exposition, and summarization, description is one of the most widely recognized of the fiction-writing modes. As stated in Writing from A to Z, edited by Kirk Polking, description is more than the amassing of details; it is bringing something to life by carefully choosing and arranging words and phrases to produce the desired effect (Polking 1990, p. 106). The most appropriate and effective techniques for presenting description are a matter of ongoing discussion among writers and writing coaches.Fiction is a form of narrative, one of the four rhetorical modes of discourse. Fiction-writing also has modes for fiction-writing: action, exposition, description, dialogue, summary, and transition (Morrell 2006, p. 127). Author Peter Selgin refers to methods, including action, dialogue, thoughts, summary, scene, and description (Selgin 2007, p. 38). Currently, there is no consensus within the writing community regarding the number and composition of fiction-writing modes and their uses.
Description is the fiction-writing mode for transmitting a mental image of the particulars of a story. Together with dialogue, narration, exposition, and summarization, description is one of the most widely recognized of the fiction-writing modes. As stated in Writing from A to Z, edited by Kirk Polking, description is more than the amassing of details; it is bringing something to life by carefully choosing and arranging words and phrases to produce the desired effect (Polking 1990, p. 106). The most appropriate and effective techniques for presenting description are a matter of ongoing discussion among writers and writing coaches.Fiction is a form of narrative, one of the four rhetorical modes of discourse. Fiction-writing also has modes for fiction-writing: action, exposition, description, dialogue, summary, and transition (Morrell 2006, p. 127). Author Peter Selgin refers to methods, including action, dialogue, thoughts, summary, scene, and description (Selgin 2007, p. 38). Currently, there is no consensus within the writing community regarding the number and composition of fiction-writing modes and their uses.
Description is the fiction-writing mode for transmitting a mental image of the particulars of a story. Together with dialogue, narration, exposition, and summarization, description is one of the most widely recognized of the fiction-w
This chapter contains information for memory compilers available in STDL80 cell library. These are
complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each
of the final building block, the physical layout, will be implemented as a stand-alone, densely packed,
pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit
design technique, these memory cells can realize extreme density and performance. In each layout
generator, we added an option which makes the aspect ratio of the physical layout selectable so that the
ASIC designers can choose the aspect ratio according to the convenience of the chip level layout.
Sign off in VLSI is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are verified to make sure it meets the desired specifications. Sign off includes the physical verification of the design, the timing verification of the design, the power verification of the design, and the electrical verification of the design. Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off
Routing in VLSI is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I/O pins.
Global Routing
first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions.
By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
Every gcell having the a number of horizontal routing resources and vertical routing resources.
Global routing assigns nets (logical connectivity not metal connectivity) to specific metal layers and global routing cells.
Track Assignment
Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows
Assigning tracks in horizontal and vertical partitions.
Rerouting all overlapped wires.
Track Assignment replaces all global routes with actual metal layers.
Although all nets are routed (not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.
Detail Routing
The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design.
The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
The main goal of detailed routing is to complete all the required interconnect without leaving shorts or spacing violations.
The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.
Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.
Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.
Placement is the process of determining the locations of circuit devices on a die
surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a
design. Traditionally, it is applied after the logic synthesis stage and before the
routing stage. Since the advent of deep submicron process technology around
the mid-1990s, interconnect delay, which is largely determined by placement,
has become the dominating component of circuit delay. As a result, placement
information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the
logic synthesis stage to perform physical synthesis and into the architecture
design stage to perform physical-aware architecture design
In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.
Physical design means --->> netlist (.v ) converted into GDSII form(layout form)
logical connectivity of cells converted into physical connectivity.
During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.
Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.
Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: A large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens
What is the Difference Between the target_library and link_library Variables?Ahmed Abdelazeem
Design Compiler already has the set target_library my_lib.db command.
Why is it necessary to also use the set link_library "* my_lib.db"
command? Can you explain the difference?
Makefiles are used to help decide which parts of a large program need to be recompiled. In the vast majority of cases, C or C++ files are compiled. Other languages typically have their own tools that serve a similar purpose as Make. Make can also be used beyond compilation too, when you need a series of instructions to run depending on what files have changed. This tutorial will focus on the C/C++ compilation use case.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
In this course, you
● Identify and apply timing arc information from a library, such as unateness, delays, and slew
● Identify cell delays from a library and calculate output slew degradation
● Use wire-load information to calculate net delays
● Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle
● Apply setup and hold checks to diagnose design violations
● Identify timing path types to calculate slack values
● Set environmental constraints, clocks constraints, and path exceptions
● Constrain a design using SDC
● Analyze reports to identify timing problems
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
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Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
EMIR.pdf
1. IR drop and Electromigration
Errors Can Break Your ASIC!
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem (ZU) EMIR ZU 2023 1 / 30
2. Table of Contents
1 Voltage (IR) Drop and Ground Bounce
2 Electromigration
3 Other related Issues
Ahmed Abdelazeem (ZU) EMIR ZU 2023 2 / 30
3. Table of Contents
1 Voltage (IR) Drop and Ground Bounce
2 Electromigration
3 Other related Issues
Ahmed Abdelazeem (ZU) EMIR ZU 2023 3 / 30
4. Introduction
IR drop: Voltage drops caused by current flowing from the power
source through the resistive power network to the on-chip devices is
called IR drop.
Ground bounce: Voltage spikes caused by current flowing from
on-chip devices though the resistive ground network to the ground
pins (or bumps)
IR drop and ground bounce combine to impact silicon performance.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 4 / 30
5. IR Drop Impacts on Setup and Hold Time
In the case where the IR drop occurs within the signal path, the signal
is slowed, potentially causing setup time violations for this signal path
In the case where IR drop occurs on a clock buffer, the clock signal
beyond this buffer is slowed, potentially causing hold time violations
for all signals clocked by this clock branch.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 5 / 30
6. How Does a Power Rail IR Drop Occur?
Ahmed Abdelazeem (ZU) EMIR ZU 2023 6 / 30
7. IR Drop Occur
The power supply (VDD and VSS) in a chip is uniformly distributed
through the metal rails and stripes which is called Power Delivery
Network (PDN) or power grid.
Each metal layers used in PDN has finite resistivity.
When current flow through the power delivery network, a part of the
applied voltage will be dropped in PDN as per the Ohm’s law
The amount of voltage drop will be V = I.R, which is called the IR
drop.
If the resistivity of metal wire is high or the amount of current
following through the power net is high, A significant amount of
voltage may be dropped in the power delivery network which will
cause a lesser amount of voltage available to the standard cells than
the actual amount of voltage applied.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 7 / 30
8. IR Continue
If V1 voltage is applied at the power port and current I is following in
a particular net which has total resistance R, then the voltage
available (V2) to the other end for the standard cell will be
V 2 = V 1–I.R (1)
Standard cells or macros sometimes do not get the minimum
operating voltage which is required to operate them due to IR drop in
power delivery network even the application of sufficient voltage in
the power port.
Voltage drop in the power delivery network before reaching the
standard cells is called IR drop.
This drop may cause the poor performance of the chip due to the
increase of delay of standard cells and may cause the functional
failure of the chip due to setup/hold timing violation.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 8 / 30
9. Types of IR drop
There are two types of IR drop in the ASIC design:
Static IR drop
Dynamic IR drop
Static IR drop is the voltage drop in the power delivery network
(PDN) when there are no inputs switching means the circuit is in the
static stage.
dynamic IR drop is the voltage drop in the power delivery network
when the inputs are continuously switching means the circuit is in a
functional state. Dynamic IR drop will depend on the switching rate
of instance.
When the inputs are switching continuously, more current would flow
in the instances and also in PDN. So there will be more IR drop in
the PDN. Therefore dynamic IR drop is more than the static IR drop.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 9 / 30
10. Static vs. Dynamic IR Drop Analysis
Ahmed Abdelazeem (ZU) EMIR ZU 2023 10 / 30
12. IR Drop Example for Chip
Ahmed Abdelazeem (ZU) EMIR ZU 2023 12 / 30
13. Reasons for IR drop:)
IR drop could occur due to various reasons but some main reasons are as
bellow.
Poor design of power delivery network (lesser metal width and more
separation in the power stripes)
inadequate via in power delivery network
Inadequate number of decap cells availability
High cell density and high switching in a particular region
High impedance of the power delivery network
Rush current
Insufficient number of voltage sources
High RC value of the metal layer used to create the power delivery
network
Ahmed Abdelazeem (ZU) EMIR ZU 2023 13 / 30
14. Method of Reducing Dynamic IR Drop
Ahmed Abdelazeem (ZU) EMIR ZU 2023 14 / 30
15. Method of Reducing Static IR Drop
The red area means a voltage drop of
more than 10% of the nominal supply
voltage. The solution is to use wider
power stripes or use more metal on
higher levels.
Additional power stripes are added to
the design and are marked in cyan and
magenta.
This IR drop plot is made after an
increase of the number of power stripes.
This plot shows a very low voltage drop,
which is required for a functional chip.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 15 / 30
16. Methods to improve IR drop
Methods to improve static IR drop
We can go for higher layers if available
Increase the width of the straps.
Increase the number of wires.
Check if any via is missing then add more via.
Methods to improve dynamic IR drop
Use de-cap cells.
Increase the number of straps
Tools used for IR drop analysis
RedHawk of Ansys.
Voltus of Cadence Design System.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 16 / 30
17. Table of Contents
1 Voltage (IR) Drop and Ground Bounce
2 Electromigration
3 Other related Issues
Ahmed Abdelazeem (ZU) EMIR ZU 2023 17 / 30
18. What is Electromigration?
Definition
is the gradual displacement of metal atoms in a semiconductor. It happens
when the current density is high enough to cause the drift of metal ions in
the direction of the electron flow.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 18 / 30
19. What is Electromigration?
Electromigration is a wear-out mechanism of metal wires.
Metal atoms migrate over a period of time, causing open circuits,
shorts circuits, or unacceptable increases in resistance.
There are two main causes of electromigration failure:
1 High (DC) current densities
2 Joule heating, which is caused by high alternating currents
These wear-out mechanisms can take extended periods of time
Ahmed Abdelazeem (ZU) EMIR ZU 2023 19 / 30
20. Causes of Electromigration
Electromigration is mechanical failure in the wire caused by frequently
varying thermal conditions.
As pulses go through the wire, the power dissipated by the wire
causes it to heat above oxide temperature
The difference in the thermal constants between the oxide and the
wire causes mechanical stress, and the wire can eventually fail
resulting in chip failure in the field.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 20 / 30
21. Electromigration Damages
Effects of EM
Depletion of atoms (Voids): Slow reduction of connectivity;
Interconnect failure
Deposition of atoms (Hillocks): Shorts
Ahmed Abdelazeem (ZU) EMIR ZU 2023 21 / 30
22. High (DC) Current Densities
Physical migration of metal atoms due to “electron wind” can
eventually create a break in a wire.
(MTTF) is an indication of the life span of an integrated circuit.
MTTF is calculated using Black’s equation as bellow.
MTTF =
A
Jn
exp(
Ea
KT
) (2)
Current density must not exceed specification
Specified as mA/ µm wire width (e.g., 1 mA/µm) or mA per via cut
EM occurs both in signal (AC=bidirectional) and power wires (DC =
unidirectional)
Much worse for DC than AC; DC occurs inside cells and in power buses
Ahmed Abdelazeem (ZU) EMIR ZU 2023 22 / 30
24. Reasons of Electromigration
Reasons of EM Violation:
High Fanout Net(Multiple fanout cells switch simultaneously, draws
larger current from driver)
Higher Driver strength Cells (delivers large current unnecessarily,
heating up the wire)
Higher Frequency (quick tarnsitions)
Narrow Metal Width.
Metal slotting (resulting into narrower widths)
Long Nets (because of larger resistance, higher localized temperature)
Ahmed Abdelazeem (ZU) EMIR ZU 2023 24 / 30
25. Prevention techniques for EM:
During the physical design, the following techniques could be used to
prevent the EM issue.
Solutions of EM Violation:
Decrease Drive’s drive Strength.
Insert Buffer on long nets.
Increase the width of wire
Adding more vias (Multi-Cut Vias)
Break the fanout (have lessar fanout)
Switch the net to higher metal layers.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 25 / 30
26. Table of Contents
1 Voltage (IR) Drop and Ground Bounce
2 Electromigration
3 Other related Issues
Ahmed Abdelazeem (ZU) EMIR ZU 2023 26 / 30
27. What Is Joule Heating?
Wire Self-Heat (WSH)
May also be called signal wire electromigration, or Joule heating, since
it is related to the power that is dissipated into the interconnect.
WSH is the rise in temperature due to the electron movement within
a conductor.
Depends on metal composition, signal frequency, wire sizes, slew
rates, and amount of capacitance driven
Self-heating = More EM
Since SH increases temperature, self-heating on a metal line can
aggravate EM effects.
SH on a line can also increase EM effects on neighboring lines.
Because self-heating contributes to electromigration, failures are
typically labeled as EM, not SH.
Ahmed Abdelazeem (ZU) EMIR ZU 2023 27 / 30
28. Hot Electron Effect (Short Channel Effect)
Caused by extremely high electric fields between source and drain
Occurs when voltages are not scaled as fast as dimensions
Electrons pick up speed in the channel
Fastest electrons damage the oxide and interface near the drain
Transistor threshold and mobility change over the life of the part, i.e.,
threshold eventually moves to a point where the device no longer
meets specifications
Ahmed Abdelazeem (ZU) EMIR ZU 2023 28 / 30
29. Analysis Output from Power Grid Analysis
Ahmed Abdelazeem (ZU) EMIR ZU 2023 29 / 30
30. Wrap up
ÕækQË@ áÔgQË@ éÊË@ Õæ„.
C
JÊ
¯ B
@ Õ
Ϊ
Ë@ áÓ Õ
æJKð@ AÓð
Ahmed Abdelazeem (ZU) EMIR ZU 2023 30 / 30