Clock Domain Crossing,

1. Clock Domain Crossing
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org
Courtesy:
1. https://anysilicon.com/clock-domain-crossing-cdc/
2. https://www.eetimes.com/understanding-clock-domain-
crossing-issues/

2. 1/27/2022
Static
Timing
Analysis
Metastability
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3. 1/27/2022
Static
Timing
Analysis
Single Clock Circuit
• The digital circuits with FFs are very
normal for digital circuits.
• The synchronous circuit has FFs and a
common clock connected with them all.
• The entire design using single clock is for
learning purpose and very elementary.
• Modern System-on-Chip (SoC) designs
continue to face increasing size and
complexity challenges
• The SoC contains number of different
blocks/IP working at different frequencies 3

4. 1/27/2022
Static
Timing
Analysis
Clock Domain Crossing
• The modern SoCs, with so many
dedicated data processing islands
usually need to transfer data between
these multiple clock domains (islands).
•When data needs to be transferred
between two different clock domains, it
will appear to be asynchronous to the
new clock domain.
• CDC is “The process of passing a
signal or vector (multi bit signal) from
one clock domain to another clock
domain.”
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5. 1/27/2022
Static
Timing
Analysis
A Clock Domain
• A part of the design that is driven by
either one clock or more clocks that
have related to each other
• Constant phase relationship between two clocks
• A clock and its variant generated by frequency
divider circuit
• A clock and its inverted clock
• CLK, its inversion, and D1 (derived from CLK) are
synchronous to each other.
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6. 1/27/2022
Static
Timing
Analysis
• Clock Domain Crossing design is a
design that has one clock asynchronous
to, or has a variable phase relation with,
another clock.
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7. 1/27/2022
Static
Timing
Analysis
Different Clock Domain
• 50MHz and 37MHz clocks (whose
phase relationship changes over time)
define two separate clock domains.
• Designs which have two unrelated
clocks (different clock frequencies) or
clocks from two different sources (even
with same frequency) are treated as
multiple clock domain designs.
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8. 1/27/2022
Static
Timing
Analysis
Synchronous Clock Domain Crossing
• Clocks which have a known phase and
frequency relationship between them
are known as synchronous clocks.
• These are essentially the clocks
originating from the same clock-root.
• A clock crossing between such clocks
is known as a synchronous clock
domain crossing.
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9. 1/27/2022
Static
Timing
Analysis
Categories of Synchronous clocks
• Clocks with the same frequency and
zero phase difference
• Clocks with the same frequency and
constant phase difference
• Clocks with different frequency and
variable phase difference
•Integer multiple clocks
•Rational multiple clocks
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Static
Timing
Analysis
Clocks with the same frequency and
zero phase difference
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Static
Timing
Analysis
Clocks with the same frequency and
constant phase difference
• Example: clock and its inverted clock
with gate delay
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12. 1/27/2022
Static
Timing
Analysis
Clocks with different frequency and
variable phase difference
• Integer multiple clocks
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13. 1/27/2022
Static
Timing
Analysis
Clocks with different frequency and
variable phase difference
• For the case of slow to fast crossings : no data
loss
• For fast to slow clock crossing Data loss
• The source data should be held constant for at
least one cycle of the destination clock.
• This can be ensured by using some control
circuit, for example, a simple finite state
machine (FSM) would work in this case. 13

14. 1/27/2022
Static
Timing
Analysis
Clocks with different frequency and
variable phase difference
• Rational multiple clocks
• In this case, the frequency of one clock is
a rational or non-integer multiple of the
other clock and the phase difference
between the active clock edges is
variable.
• Unlike the situation where one clock is
an integer multiple of the other, here the
minimum phase difference between the
two clocks can be very small- small
enough to cause metastability.
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15. 1/27/2022
Static
Timing
Analysis
Asynchronous Clock Domain
Crossing
• Clocks which do not have a known phase
or frequency relationship between them
are known as asynchronous clocks.
• Whenever there is a clock crossing
between two asynchronous clocks, their
active edges can arrive very close
together leading to metastability. Here
the phase difference between the clocks
can be variable and unlike synchronous
clocks it is unpredictable.
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16. 1/27/2022
Static
Timing
Analysis
Simulation and STA is not enough
for clock domain crossing
• Within one clock domain, proper static
timing analysis (STA) can guarantee
that data does not change within clock
setup and hold times. When signals
pass from one clock domain to another
asynchronous domain, there is no way
to avoid such scenario since data can
change at any time.
1
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17. 1/27/2022
Static
Timing
Analysis
Issues with Clock Domain Crossing
1. Metastability
2. Data Loss
3. Data Incoherency
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18. 1/27/2022
Static
Timing
Analysis
Meta-stability
• i.e. unstable or intermediate state
• For digital circuits, it means that a FF
can enter a state where output might
not have reached to its final expected
value and can oscillate between 0 or 1.
• The signal will stabilize after some
time but that depends on FF type and
the PVT conditions.
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Static
Timing
Analysis
Metastability
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Static
Timing
Analysis
Metastability
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Static
Timing
Analysis
The consequences of Metastability
1. If the unstable data is fed to several other
places in the design, it may lead to a high
current flow and even chip burnout in the
worst case.
2. Different fan-out cones may read different
values of the signal, and may cause the
design to enter into an unknown functional
state, leading to functional issues in the
design.
3. The destination domain output may settle
down to the new value or may return to the
old value. However, the propagation delay
could be high leading to timing issues.
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22. 1/27/2022
Static
Timing
Analysis
Metastability is unavoidable in CDC
• In a multi-clock design, meta-stability
is inevitable, but there are certain
design techniques that help to avoid
the chance of getting meta-stable.
2
2

23. 1/27/2022
Static
Timing
Analysis
Synchronizer
• Synchronizer allows sufficient time for the
oscillations to settle down and ensure that a
stable output is obtained in the destination
domain.
• Types of Synchronizers
• Multiflop synchronizer
• For single and multi-bit control signals
and single bit data signals
• MUX recirculation
• Handshake
• FIFO
• All above three for multi-bit data signals
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24. 1/27/2022
Static
Timing
Analysis
2-flop
Synchronizer
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25. 1/27/2022
Static
Timing
Analysis
What if signal does not get settled in
one clock cycle?
• In a 2-FF synchronizer, the first flip-flop
samples the asynchronous input signal into the
destination clock domain and waits for a full
destination clock cycle to permit any meta-
stability on the stage-1 output signal to decay,
then the stage-1 signal is sampled by the same
clock into a second stage flip-flop, with the
intended goal that the stage-2 signal is now a
stable and valid signal synchronized into the
destination clock domain. It is theoretically
possible for the stage-1 signal to still be
sufficiently meta-stable by the time the signal is
clocked into the second stage to cause the
stage-2 signal to also go meta-stable.
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26. 1/27/2022
Static
Timing
Analysis
Mean Time Between Failure (MTBF) of Metastability
• Note that the meta-stability is a probabilistic phenomenon.
• The meta-stable output converges to a stable value with time.
Therefore, even if the input to the stage-2 FF still remains
meta-stable, the probability that the output of the stage-2 FF
will remain meta-stable for a full destination clock cycle is
asymptotically close to zero.
• This calculation of the probability of the time between
synchronization failures (MTBF) is a function of multiple
variables including the clock frequencies used to generate the
input signal and to clock the synchronizing flip-flops.
• For most synchronization applications, a 2-FF synchronizer is
sufficient to remove all likely meta-stability.
• However for certain very high speed clock frequencies, the
MTBF can be increased more by either using special cells
provided in technology libraries or/and using more than 2
stages of the FFs as synchronizers (3 or 4 stages of FFs).
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27. 1/27/2022
Static
Timing
Analysis
Limitation of 2FF Synchronizer
• These 2 FF synchronizer circuits work
very well for most of the applications that
involve single bit control signals and
where the input toggle rate is less than
the destination clock frequency
• There will be no data loss if destination
clock frequency is more than 1.5 times
of source clock frequency.
• If the source and destination clock
frequency are almost same or destination
clock frequency is slow, then source
must keep its value stable for destination
to capture it, before changing to next
value or the data will be lost.
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28. 1/27/2022
Static
Timing
Analysis
Data Loss
• As long as each transition on the source signal is
captured in the destination domain, data is not
lost.
• Whenever a new source data is generated, it may
not be captured by the destination domain in the
very first cycle of the destination clock because of
metastability.
• In order to ensure this, the source data should
remain stable for some minimum time, so that
the setup and hold time requirements are met
with respect to at least one active edge of
destination clock.
• There may not be a cycle by cycle correspondence
between the source and destination domain data.
Whatever the case, it is important that each
transition on the source data should get captured
in the destination domain.
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29. 1/27/2022
Static
Timing
Analysis
Input Data Stability to Avoid Data
Loss
• Every transition on the input signal needs to be
correctly propagated to the destination domain.
• The input signal needs to hold its value a
minimum amount of time such that there is at
least a single destination sampling clock edge,
which samples the input value correctly (No
setup/hold violation)
2
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30. 1/27/2022
Static
Timing
Analysis
• If there is sufficient time between the transition on
data A and the active edge of clock C2, the data is
captured in the destination domain in the first cycle
of C2.
• But if the active clock edges of C1 and C2 arrive
close together, the first clock edge of C2, which
comes after the transition on source data A, is not
able to capture it. The data finally gets captured by
the second edge of clock C2 30

31. 1/27/2022
Static
Timing
Analysis
Example of Data loss
• C1= 2 X C2,
• Data sequence A generated on +ve edge of C1 is
00110011
• Data captured on +ve edge of C2 is 0101.
• Overall all transitions captured so no data loss
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32. 1/27/2022
Static
Timing
Analysis
Example of Data loss
• C1= 2 X C2,
• Data sequence A generated on +ve edge of C1 is
00101111
• Data captured on +ve edge of C2 is 0011.
• Overall all transitions captured so no data loss
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33. 1/27/2022
Static
Timing
Analysis
Data Incoherency
• Consider a case where multiple signals (e.g.
data bus, vector) are being transferred from
one clock domain to another and each signal
is synchronized separately using a multi-flop
synchronizer.
• If all the signals are changing simultaneously
and the source and destination clock edges
arrive close together, some of the signals may
get captured in the destination domain in the
first clock cycle while some others may be
captured in the second clock cycle by virtue of
Metastability.
• This may result in an invalid combination of
values on the signals at the destination side.
Data coherency is said to have been lost in
such a case.
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34. 1/27/2022
Static
Timing
Analysis
Data incoherency
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Static
Timing
Analysis
3
5
The natural way to transfer a vector control signal is
to model each bit of the vector to be separately
synchronized by a FF synchronizer
Sig wants to change its value from "000" to "101" (both indicate valid
states). However, it ends up in invalid state “100”.
Example : Data Incoherency

36. 1/27/2022
Static
Timing
Analysis
Solution to Data Incoherency
• The problem results because all the bits are not
changing to a new state in the same cycle of destination
clock.
• If all the bits either retain their original value or change
to the new value in the same cycle, then the design
either remains in the original state or goes to a correct
new state.
• Now, if the circuit is designed in such a way that while
changing the design from one state to another, only one
bit change is required, then either that bit would change
to a new value or would retain the original value.
• Since all the other bits have the same value in both the
states, the complete bus will either change to the new
value or retain the original value in this case.
• This in turn implies that if the bus is Gray-encoded, the
problem would get resolved and an invalid state would
never be obtained.
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37. 1/27/2022
Static
Timing
Analysis
Gray Encoding
• Use Gray code when crossing a clock
domain boundary.
• A Gray code ensures that only a single
bit changes as the bus counts up or
down or for two successive states.
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38. 1/27/2022
Static
Timing
Analysis
Gray Encoding
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Static
Timing
Analysis
Limitations of Gray Code for Data
incoherency
• The Gray code technique is applicable
only for control busses.
• The individual bits of a data bus can
change randomly while changing clock
boundaries. It may not be possible to
Gray-encode the data busses.
• Using synchronizers/gray code to
handle the passing of data bus is
generally unacceptable
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40. 1/27/2022
Static
Timing
Analysis
Synchronization Methods for Data
Signals over clock domain
• Using MUX based synchronizers.
• Using Handshake signals.
• Using FIFOs (First In First Out memories)
to store data with one clock domain and to
retrieve data with another clock domain.
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0

41. 1/27/2022
Static
Timing
Analysis
MUX Recirculation Synchronizer
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42. 1/27/2022
Static
Timing
Analysis
1. A EN control signal generated into source domain
is sent to destination domain first and is being
synchronized in the destination domain using a
multi-flop synchronizer.
2. The synchronized EN (EN_Sync) signal is applied
to MUX to allow the source data bus values A[1:0]
to transfer to destination flipflops.
3. Individual bits of the bus are not synchronized
separately, and hence there is no data incoherency
4. A[1:0] should be held constant while EN is being
synchronized.
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43. 1/27/2022
Static
Timing
Analysis
Handshaking
• In handshake technique, the source domain sends the
“request” signal to destination domain which uses a 2-
FF synchronizer. Once the destination domain receives
the request, it sends an “ack” signal to the source
domain which uses 2-FF synchronizer to synchronize it.
The ack signal indicates to the source that destination
has received the value and source can update its value.
There are many implementation versions of the
handshake mechanism, but the principle remains the
same – synchronizing the request and ack signals. The
same technique can be applied to do a data bus transfer
from source clock domain to destination clock domain.
The request will indicate a new value on the bus where
as ack will indicate that data bus can be updated.
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Static
Timing
Analysis
Handshaking Data between Clock
Domains
4
4

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Static
Timing
Analysis
Limitation of Handshaking
• The above mechanism does have one
drawback in terms of bandwidth usage of
the interface. For handshaking
mechanism, the data bus cannot be
updated while receiving the ack signal.
For applications where this is a
bottleneck, this can be solved by using
Dual Clock Asynchronous FIFO.
Correctly designed FIFOs can increase
bandwidth across the interface while still
maintaining reliable communication
across channels.
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46. 1/27/2022
Static
Timing
Analysis
Passing Data by FIFO between Clock Domains
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Static
Timing
Analysis
User-defined Synchronizers
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48. 1/27/2022
Static
Timing
Analysis
Structural Analysis to Identify CDC
Signals
• The most important task of any CDC
structural analyzer is to find out all
the signals (CDC) that cross clock
boundaries.
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8

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Static
Timing
Analysis
Convergence in the Crossover Path
4
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Static
Timing
Analysis
Divergence in the Crossover Path
• Design styles which allow divergent
logic on a CDC signal to multiple
synchronization paths, may cause
functional errors.
5
0

51. 1/27/2022
Static
Timing
Analysis
Divergence of Meta-stable Signal
• Using a meta-stable signal in a design
can be erroneous. Therefore multiple fan-
out of the output of the first FF of a FF
synchronizer can cause functional
errors.
5
1

52. 1/27/2022
Static
Timing
Analysis
convergence of Synchronized Signals
• When a signal goes meta-stable, a
synchronizer settles it down, but
cannot guarantee the precise number
of cycles before the valid signal is
available in the receiving clock
domain.
5
2

53. 1/27/2022
Static
Timing
Analysis
Conclusion
• A CDC signal is a signal latched by a flip-
flop (FF) in one clock domain and
sampled in another asynchronous clock
domain.
• Transferring signals between
asynchronous clock domains may lead to
setup or hold timing violations of flip-
flops.
• These violations may cause signals to be
meta-stable.
5
3

54. 1/27/2022
Static
Timing
Analysis
Conclusion
• Even if synchronizers could eliminate the meta-
stability, incorrect use, such as convergence of
synchronized signals or improper synchronization
protocols, may also result in functional CDC errors.
• Functional validation of such SoC designs is one of
the most complex and expensive tasks.
• Simulation on register transfer level (RTL) is still
the most widely used method. However, standard
RTL simulation can not model the effect of meta-
stability.
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4

55. 1/27/2022
Static
Timing
Analysis
CDC Tips
1. Eliminate the combinatorial paths between two
clock domains when signal is transferred from
one clock domain to another clock domain.
2. FFs forming the synchronizer circuits must be
placed closed to each other to allow smallest
possible clock skew between them.
3. Never synchronize the same signal in more than
one place.
4. Do not use Dual FF synchronizer scheme for a
bus of data. Use handshaking technique.
5. It is good to invest time in good CDC design
techniques rather than spending time in debug.
CDC issues are very hard to debug to start with
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56. Thanks!
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