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13_DVD_Latch-up_prevention.pdf

Usha Mehta
Usha Mehta
Usha MehtaProfessor at Institute of Technology, Nirma University, Ahmedabad

CMOS Latch Up

13_DVD_Latch-up_prevention.pdf

1 of 16
11/22/2023 Latch-up and Prevention 1
Latch-up and Its Prevention
Usha Mehta
usha.mehta@nirmauni.ac.in
11/22/2023 Latch-up and Prevention 2
What is Latch-up?
• Latchup is the creation of a low impedance path
between the power supply rails (which should neve
exist in CMOS).
• Because of PARACITIC Bipolar transistors (BJTs) in
CMOS ICs
• Triggered when applying voltage or current input,
output, I/O pin, over voltage on Vdd pin.
22-11-2023 Usha Mehta 2
11/22/2023 Latch-up and Prevention 3
• Temporary Latch-Up
• A temporary or transient latchup occurs only while the
pulse stimulus is connected to the integrated circuit and
returns to normal levels once the stimulus is removed.
• Permanent/True Latch-Up
• A true latchup remains after the stimulus has been
removed and requires a power supply shut down to
remove the low impedance path between the power supply
rails
22-11-2023 Usha Mehta 3
11/22/2023 Latch-up and Prevention 4
How does Latch-up occur?
• Latchup is the regenerative process that can occur in a pnpn
structure (SCR-silicon controlled rectifier) formed by a parasitic
npn and a parasitic pnp transistor.
• Important concepts:
• To avoid latchup, vPNPN ≥ VS
• Once the pnpn structure has latched up, the large current
required by the above i-v characteristics must be provided
externally to sustain latchup
• To remove latchup, the current must be reduced below the
holding current
22-11-2023 Usha Mehta 4
11/22/2023 Latch-up and Prevention 5
Latch-Up and its Prevention
• Latch is the generation of a low-
impedance path in CMOS chips
between the power supply and the
ground rails due to interaction of
parasitic pnp and npn bipolar
transistors. These BJTs for a
silicon-controlled rectifier with
positive feedback and virtually
short circuit the power and the
ground rail.
• This causes excessive current
flows and potential permanent
damage to the devices.
• Analysis of the a CMOS Inverter
CMOS depicting the parasitics.
11/22/2023 Latch-up and Prevention 6
Latch-Up Continued
• The equivalent circuit shown has
Q1 being a vertical double
emmitter pnp transistor whose
base is formed by the n-well with a
high base to collector current gain
(b1).
• Q2 is a lateral double emitter npn
transistor whose base is formed by
the p-type substrate.
• Rwell represents the parasitic
resistance in the n-well structure
whose value ranges from 1KW to
20kW.
• The substrate resistance Rsub
depends on the substrate
structure.
• Assume the Rwell and Rsub are
significantly large so that they
cause open circuit connections,
this results in low current gains
and the currents would be
reverse leakage currents for both
the npn and pnp transistors.
• If some external disturbance
occurs, causing the collector
current of one of the parasitic
transistors to increase, the
resulting feedback loop causes
the current perturbation to be
multiplied by b1.b2
Ad

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13_DVD_Latch-up_prevention.pdf

  • 1. 11/22/2023 Latch-up and Prevention 1 Latch-up and Its Prevention Usha Mehta usha.mehta@nirmauni.ac.in
  • 2. 11/22/2023 Latch-up and Prevention 2 What is Latch-up? • Latchup is the creation of a low impedance path between the power supply rails (which should neve exist in CMOS). • Because of PARACITIC Bipolar transistors (BJTs) in CMOS ICs • Triggered when applying voltage or current input, output, I/O pin, over voltage on Vdd pin. 22-11-2023 Usha Mehta 2
  • 3. 11/22/2023 Latch-up and Prevention 3 • Temporary Latch-Up • A temporary or transient latchup occurs only while the pulse stimulus is connected to the integrated circuit and returns to normal levels once the stimulus is removed. • Permanent/True Latch-Up • A true latchup remains after the stimulus has been removed and requires a power supply shut down to remove the low impedance path between the power supply rails 22-11-2023 Usha Mehta 3
  • 4. 11/22/2023 Latch-up and Prevention 4 How does Latch-up occur? • Latchup is the regenerative process that can occur in a pnpn structure (SCR-silicon controlled rectifier) formed by a parasitic npn and a parasitic pnp transistor. • Important concepts: • To avoid latchup, vPNPN ≥ VS • Once the pnpn structure has latched up, the large current required by the above i-v characteristics must be provided externally to sustain latchup • To remove latchup, the current must be reduced below the holding current 22-11-2023 Usha Mehta 4
  • 5. 11/22/2023 Latch-up and Prevention 5 Latch-Up and its Prevention • Latch is the generation of a low- impedance path in CMOS chips between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and the ground rail. • This causes excessive current flows and potential permanent damage to the devices. • Analysis of the a CMOS Inverter CMOS depicting the parasitics.
  • 6. 11/22/2023 Latch-up and Prevention 6 Latch-Up Continued • The equivalent circuit shown has Q1 being a vertical double emmitter pnp transistor whose base is formed by the n-well with a high base to collector current gain (b1). • Q2 is a lateral double emitter npn transistor whose base is formed by the p-type substrate. • Rwell represents the parasitic resistance in the n-well structure whose value ranges from 1KW to 20kW. • The substrate resistance Rsub depends on the substrate structure. • Assume the Rwell and Rsub are significantly large so that they cause open circuit connections, this results in low current gains and the currents would be reverse leakage currents for both the npn and pnp transistors. • If some external disturbance occurs, causing the collector current of one of the parasitic transistors to increase, the resulting feedback loop causes the current perturbation to be multiplied by b1.b2
  • 7. 11/22/2023 Latch-up and Prevention 7 Latch-up Continued • This event triggers the silicon- controlled rectifier and each transistor drives the other with positive feedback eventually creating and sustaining a low impedance path between power and the ground rails resulting in latch-up. • For this condition if b1 *b1 is greater than or equal to 1 both transistors will continue to conduct saturation currents even after the triggering perturbation is no longer available. • Some causes for latch-up are: • Slewing of VDD during start-up causing enough displacement currents due to well junction capacitance in the substrate and well. • Large currents in the parasitic silicon-controlled rectifier in CMOS chips can occur when the input or output signal swings either far beyond the VDD level or far below VSS level, injecting a triggering current. Impedance mismatches in transmission lines can cause such disturbances in high speed circuits. • Electrostatic Discharge stress can cause latch-up by injecting minority carriers from the clamping device in the protection circuit into either the substrate or the well. • Sudden transient in power or ground buses may cause latch-up.
  • 8. 11/22/2023 Latch-up and Prevention 8 Guidelines For Avoiding Latch-Up • Reduce the BJT gains by lowering the minority carrier lifetime through Gold doping of the substrate (solution might cause excessive leakage currents). • Use p+ guardband rings connected to ground around nMOS transistors and n+ guard rings connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJT. • Place substrate and well contacts as close as possible to the source connections of the MOS transistors to reduce the values of Rw and Rsub. (solution to be used in your designs) • Place source diffusion regions for the pMOS transistors so that they lie along equipotentials lines when currents flow between VDD and p-wells. • Avoid forward biasing of the source/drain junctions so as not to inject high currents , this solution calls for the use of slightly doped epitaxial layer on top of the heanily doped substrate and has the effect of shunting the lateral currents from the vertical transistor through the low resistance substrate.
  • 9. 11/22/2023 Latch-up and Prevention 9 How does Latch-up sustains? • The loop gain of the relevant BJT configuration must exceed unity. βn βp ≥ 1 • A bias condition must exist such that both bipolars are turned on long enough for current through the “SCR” to exceed its switching current. • The bias supply and associated circuits must be capable of supplying the current at least equal to the switching current and at least equal to the holding current to maintain the latched state. 22-11-2023 Usha Mehta 9
  • 10. 11/22/2023 Latch-up and Prevention 10 Latch-up in CMOS IC 22-11-2023 Usha Mehta 10 Lateral BJTs LT1 and LT2 Vertical BJTs VT1 and VT2
  • 11. 11/22/2023 Latch-up and Prevention 11 • When Vout > Vdd 22-11-2023 Usha Mehta 11
  • 12. 11/22/2023 Latch-up and Prevention 12 Shallow Trench Isolation to reduce latch- up 22-11-2023 Usha Mehta 12
  • 13. 11/22/2023 Latch-up and Prevention 13 Guard Rings to prevent Latch-Up 22-11-2023 Usha Mehta 13
  • 14. 11/22/2023 Latch-up and Prevention 14 Guard Ring Collects Carriers 22-11-2023 Usha Mehta 14
  • 15. 11/22/2023 Latch-up and Prevention 15 Inverter with Guard Ring 22-11-2023 Usha Mehta 15
  • 16. 11/22/2023 Latch-up and Prevention 16 22-11-2023 Usha Mehta 16