This document provides an overview of VLSI design and testing processes. It discusses various stages in the design flow from behavioral to physical design. It describes the importance of verification, validation, and testing at each stage to detect errors and ensure quality. These include simulation, emulation, formal methods, probe testing, and burn-in testing. Factors like process variations that affect speed are addressed through speed binning. The document emphasizes that testing is crucial throughout the design and manufacturing cycles to find faults and prevent defective chips from reaching customers.
Introduction of testing and verification of vlsi designUsha Mehta
This slides are introductory slides for the course testing and verification of VLSI Design which cover the basics of Why, Where, When and How of VLSI design testing
Introduction of testing and verification of vlsi designUsha Mehta
This slides are introductory slides for the course testing and verification of VLSI Design which cover the basics of Why, Where, When and How of VLSI design testing
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
1) A technique to refine at-speed launch and capture clock edge placement by applying several at-speed shift cycles before the launch.
2) Extension to LOS.
3) Once the scan chains are fully loaded, the controller shifts to the burst phase, in which the true functional clocks are applied. The scan chains are still left in the shift mode while the scan data rotates through the scan chains for a few cycles. Then a single capture cycle is applied and the data is shifted out.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
1) A technique to refine at-speed launch and capture clock edge placement by applying several at-speed shift cycles before the launch.
2) Extension to LOS.
3) Once the scan chains are fully loaded, the controller shifts to the burst phase, in which the true functional clocks are applied. The scan chains are still left in the shift mode while the scan data rotates through the scan chains for a few cycles. Then a single capture cycle is applied and the data is shifted out.
Oplægget blev holdt ved et seminar i InfinIT-interessegruppen Processer & IT Nord den 5. marts 2014. Læs mere om interessegruppen her: http://infinit.dk/dk/interessegrupper/processer_og_it/processer_og_it.htm
Testing- Fundamentals of Testing-Mazenet solutionMazenetsolution
For Youtube Videos: bit.do/sevents
Why testing is necessary,Fundamental test process, Psychology of testing, Re-testing and regression testing,
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On large enterprise projects, the user acceptance test (UAT) is often envisioned to be a grand event where the users accept the software, money is paid, and the congratulations and champagne flow freely. UAT is expected to go well, even though some minor defects may be found. In reality, acceptance testing can be a very political and stressful activity that unfolds very differently than planned. Randy Rice shares case studies of UAT variances on projects he has facilitated and what can be done in advance to prepare for an acceptance test that is a beauty pageant rather than a monster's ball. Learn how UAT can go in a totally unexpected direction and what you can do to prepare for that situation. Understand the project risks when UAT is performed only as an end-game activity. Learn how to be flexible in staying in sync with stakeholders and user expectations—even test coverage is reduced to its bare minimum.
An engineering perspective on biometric sensor integration in wearablesValencell, Inc
Integrating biometric sensors into wearables can be one of the most challenging aspects of building a wearable or hearable.
Valencell’s engineering team has been involved in more than 50 different biometric wearable projects. We’ve gathered up the most common questions our engineers receive during the product design and development process, and VP of Engineering, Dr. Mike Aumer, will share our answers to those questions.
Designing the Enterprise for Manufacturingsc0ttruss
Britain has a long history of manufacturing, and whilst the decline of the sector is well documented, applying the basic principles of traditional manufacturing to the “whitecollar” office environment is the new manufacturing. This talk will take you through the basic building patterns of manufacturing, looking at vendor selection/audits, the QA process, understanding of basic costings, discovering if the “products” are low volume, High mix, or low mix high volume and what the implications of design for manufacture would be in such an environment. Also, how to apply these basic patterns to the modern software driven “Office ” world. This is part one of a two part talk, the second one being “Preparing the Enterprise for Manufacturing”.
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High performance teams are defined by their ability to deliver software faster, with higher quality and reliability. A key ingredient is a Continuous Delivery process that allows you to deliver features to production seamlessly. Once you embrace Continuous Delivery, it is important to measure the effectiveness of your CD workflow.
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This is the first session from a series of sessions on Verification of VLSI Design. It focus on the basic flow of verification in context of system design flow, types of verification, Functional, formal and semi-formal verification, Simulation, Emulation and Static Timing Analysis.
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The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
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We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
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2. Acknowledgement…..
This presentation has been summarized from
various books, papers, websites and
presentations on VLSI Design and its various
topics all over the world. I couldn’t item-wise
mention from where these large pull of hints and
work come. However, I’d like to thank all
professors and scientists who created such a
good work on this emerging field. Without those
efforts in this very emerging technology, these
notes and slides can’t be finished.
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Mehta
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6. • Design Errors
• Misinterpretation of specification
• Fabrication Errors
• Wrong component
• Incorrect Wiring
• Fabrication Defects
• Imperfect Process Variations
• Physical Failure
• During life time of a system 25-
01-
202
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9. Role of Testing in General
• Verification
• will any fault occur?
• Validation
• will fault occur during mass production?
• Detection
• Is there any fault? Yes or no?
• Diagnosis
• Where is the fault?
• Device Characterization
• Why the fault occurred? (Is design wrong or test process wrong?)
• Failure Mode Analysis (FMA)
• How that fault can be prevented? (Is manufacturing process wrong?)
• Burn-In
• Will it work for longer life?
• Speed Binning
• What is the speed of device?
• Acceptance Testing/Incoming Inspection
• Should I use it in my system?
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Dr
Usha
Mehta
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10. Verification
• Verifies the correctness of Design
• Performed once prior to manufacturing
process
• Performed by simulation, hardware
emulation or formal methods
• Responsible for quality of design
• Like sonography used for unborn baby
during pregnancy
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Dr
Usha
Mehta
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11. Validation
Verification Testing/Characterization / Design Debug
• After the first lot of prototypes are
manufactured, IC goes through, design
validation/pilot-run stage.
• It checks that either the fabrication process
was correct and fabricated IC is correct. ( Here
it is assumed that design was error free)
• Also verifies the correctness of test procedure.
• AC, DC, Functional Test
• Probing internal chip nodes also
• Special tools like scanning electron
Microscope, electron beam scanner, artificial
intelligent technique etc, are used
• Like Newborn sreening tests for baby
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Dr
Usha
Mehta
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12. Diagnosis
• Identify the fault that exists in system.
• Which fault is there (type of fault)?
• Where is that fault (fault location)?
• Like after a set of pathological test, the
doctor diagnosis your disease.
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Dr
Usha
Mehta
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13. Device Characterization
• Determination and correction of errors
in device and/or test procedure
• So that the next lot of IC will be error
free.
• Like doctor writes a prescription of
medicine to cure your disease.
• Here there is a difference between man
and IC!!!!!!!!!
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Dr
Usha
Mehta
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14. Failure Mode Analysis
• Why/How/when the fault had occurred?
• Determine the manufacturing process
errors that may have caused the fault.
• Like determining why that disease
occurred and find the preventive actions
(bad health /food habits) which created
disease
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Dr
Usha
Mehta
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15. Detection (testing in general…)
• Does any of the fault exists?
• Which, why, how, where, when is out of scope here.
• Only YES/NO. Go/No Go test for IC to be shipped to market
or not.
• At fabrication unit
• For all fabricated IC
• Less comprehensive than characterization
• Test should have high fault coverage, low cost and minimum
test time
• Are you completely fit? Does any of the disease
there?
• Like medical test for army ( if fit then go, otherwise
no go)
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Dr
Usha
Mehta
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16. Burn-In/Stress Test
• To stress the chip to accelerate the
failure mechanism
• Some chip passes the production test
but will fail very quickly thereafter
• To increase temp and/or voltage while
applying test patterns
• Infant Mortality Failures: 10-30 Hrs
• Freak Failure: 100-1000Hrs
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Dr
Usha
Mehta
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17. Acceptance Testing/
Incoming Inspection
• Customer performs this test
• Like universal tester to test the IC at our
Digital Electronics Labs
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Dr
Usha
Mehta
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18. Place of Verification in Design Flow
• Specification
• Finalization of
specification
• Behavioural
Description/RTL code
• Functional Verification
• Gate level netlist
• Static timing analysis
• Circuit level
• Propagation delay
• Physical Domain
• Layout vs Schematic
(LVS)
• During Fabrication
• Wafer testing
• Pilot lot production
• Validation
• Mass production
• Testing
• Burn-In
• Speed Binning
• Yield loss
• Diagnosis
• Failure Mode
Analysis
• Before use
• Acceptance/Incomin
g Testing
• In-System
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Dr
Usha
Mehta
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19. Speed Binning
• CMOS is made of pMOS and nMOS.
• Generally, the design is such a way that
both of them have same speed
• But the performance can vary because
of PVT
• Process variations (P), Supply Voltage (V),
Temperature (T)
• But during fabrication process, due to
process variations speed may be
degraded
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Dr
Usha
Mehta
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20. Speed Binning……
Process Variations
• Variations in the process parameters
can be impurity concentration densities,
oxide thicknesses and diffusion depths.
• This introduces variations in the sheet
resistance and transistor parameters
such as threshold voltage.
• Dimension variations of the devices, are
mainly resulted from the limited
resolution of the photolithographic
process.
• This causes (W/L) variations in MOS
transistors
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Dr
Usha
Mehta
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21. Speed Binning…..
Process Corners
• There are five possible corners of an n vs. p
mobility graph:
• typical-typical (TT) (not really a corner !), fast-
fast (FF), slow-slow (SS), fast-slow (FS), and
slow-fast (SF).
• TT, FF and SS (even corners)
• Both types of devices are affected evenly, and generally
do not adversely affect the logical correctness of the
circuit.
• FS, SF ("skewed" corners)
• one type of FET will switch much faster than the
other, and this form of imbalanced switching can
cause one edge of the output to have much less
slew than the other edge.
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Dr
Usha
Mehta
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22. Verification
• On Design
(functionality,
estimated speed)
• Pre-silicon
• One time
• Methods:
• Simulation
• Emulation
• formal methods
• A Design Bug
• Makes all Fabricated
IC useless
Detection/Testing
• On Device
(manufactured
hardware)
• Post-Silicon
• On each and every IC
being fabricated
• Methods:
• Test Generation
• Test Application
• A fabrication defect
• May cause all ICs or
Some of the ICs
useless. 22
Dr
Usha
Mehta
25-01-2022