Introduction: Digital VLSI Design

1. Digital VLSI Design
Flow
Dr Usha Mehta
usha.mehta@nirmauni.ac.in
1/24/2019

2. Acknowledgement
This presentation has been summarized from
various books, papers, websites and presentations
related to the topic all over the world. I couldn’t
remember where these large pull of hints and work
come from. However, I’d like to thank all professors
and scientists who created such a good work on
this emerging field. Without those efforts in this
very emerging technology, these notes and slides
can’t be finished.

3. • Suppose you have an
idea/requirement/application….
• And you want to develop a Electronic System
that works for it..

4. Typical Considerations…
• Cost Constraints
• Design Time
• Component Supply
• Prior Experience
• Training
• Contact Arrangement ( User Constraints)
• Size/Volume/Weight Constraints
• Power Source
• Power Consumption Constraint
• Rapid prototyping
• In-service updatebility/product upgrade

5. The system will include
• Mechanical Parts
Package etc
• Electronics Parts
PCB
IC
Components
Wires
Connectors

6. Integrated Circuits
• Based on Application
Linear (Analog) – Digital - Mixed
• Based on Fabrication Technology
Monolithic - Hybrid
• Based on Device
BJT-CMOS
• Based on Device Count
SSI-MSI-LSI-VLSI-ULSI

7. When you are system developer….
You may use
• Standard Product ICs
Off – the-self electronic component that you
purchase and use
• Application Specific Integrated Circuits (ASICs)
Specifically designed by you for your application
requirements

8. Digital ICs
1/24/2019

9. What the Digital ICs do?
• Fixed Functionality
• Processor
• Memory
• PLD

10. How the Digital ICs do?

11. Integrated Circuits
• Standard Products-ASIC
• Fixed Logic-Programmable
• Analog-Digital-Mixed Mode
• Memory-Processor
• CPLD-FPGA-Processor
• Microprocessor-Microcontroller-Digital Signal
Processor
• ASIC-SoC-NoC
• ……

13. ASIC Design Methodologies
• Full Custom
Consider circuit performance vs design time
Design + Fabrication + testing time
Technology Window
• Semi Custom
Updateability
Divide and conquer…..
Use readily available….
• Programmable
Reprogrammable/erasable
Field Programmable
Very fast…

14. Design Hierarchy
Top Down Design
• The initial work is quite abstract and
theoretical and there is no direct connections
to silicon until many steps have been
completed.
• Acceptable in modern digital system design
• Co-designing with H/W-S/W is critical
Bottom-Up Design
• Starts at the silicon or circuit level and builds
primitive units such as logic gates, adders and
registers as first step

15. Top-Down Approach

16. specification
behavior
register-
transfer
logic
circuit
layout
English
Executable
program
Sequential
machines
Logic gates
transistors
rectangles
Throughput,
design time
Function units,
clock cycles
Literals,
logic depth
nanoseconds
microns
Design Abstractions
specification
behavior
register-
transfer
logic
circuit
layout
specification
behavior
register-
transfer
logic

17. Y Chart by D Gajski

19. Specification
• Specification of the size, speed, power and
functionality of the VLSI system.
• Decisions on the architecture, e.g., RISC/CISC, #
of ALU’s, pipeline structure, cache size, etc. Such
decisions can provide an accurate estimation of
the system performance, die size, power
consumption, etc.
Architectural Design

20. Functional/Behavioural Design
• Identify main functional units and their
interconnections. No details of implementation.
• Functional design is generally done with HDL

21. Register Transfer Level
+
+
0010
0001
0100
0011
• Components, data types
• Design the logic, e.g., Boolean expressions,
control flow, word width, register
allocation, etc.
• RTL is expressed in a HDL mostly
synthesized from behavioral description

22. Logic Level
• Discrete Level, Discrete Time
• Design the circuit including gates, transistors,
interconnections, etc. The outcome is called a
netlist.
• Homework
ISCAS Gate level
Netlist

23. Circuit level
• Continuous Voltage, Continuous time

24. Layout
• Convert the netlist into a geometric
representation. The outcome is called a layout.

25. Terminology…

26. Few more words…
• Circuit Partitioning – Partition a large circuit into
sub-circuits (called blocks). Factors like #blocks,
block sizes, interconnection between blocks, etc., are
considered.
• Floorplanning – Set up a plan for a good layout.
Place the modules (modules can be blocks,
functional units, etc.) at an early stage when details
like shape, area, I/O pin positions of the modules,
…, are not yet fixed.
• Placement – Exact placement of the modules
(modules can be gates, standard cells, etc.) when
details of the module design are known. The goal is
to minimize the delay, total area and interconnect
cost.

27. • Routing – Complete the interconnections between
modules. Factors like critical path, clock skew,
wire spacing, etc., are considered. Include global
routing and detailed routing.
• Compaction – Compress the layout from all
directions to minimize the total chip area.
• Verification – Check the correctness of the
layout. Include DRC (Design Rule Checking),
circuit extraction (generate a circuit from the
layout to compare with the original netlist),
performance verification (extract geometric
information to compute resistance, capacitance,
delay, etc.)

28. Cont….
• Logic Synthesizer
Translation from RTL specification to netlist
Adequate for the design that do not have
critical performance parameter
Provides room to make design improvement
Understanding of device architecture is
necessary
• Gate Level Simulation
To ensure correctness of synthesis
translation
Vendor supplied parameters are used to
simulate the actual target device parameters

29. Cont…
• Extraction
 Actual resistance and capacitance figures modelled
for interconnections are extracted to simulate timing
performance
• Post Layout Simulation
 Functionality taking care of timings
 Time extraction imported
 Both gate and interconnection delays are considered
• Back Annotation
 To update the initial circuit data with information
that was obtained later in the design cycle
 Passing the information related to the extra load that
may occur in practice

30. Cont…
• Extended Testing
For ASIC, GA, SoG.
Not for FPGA
• Device Programming
Via JTAG port
For FPGA

31. Hierarchical Des
• Regularity
• Modularity
• Locality
• Does it mean that SRAM/DRAM is much
ahead compared to microprocessor??
Memory wall……

32. Processor vs. Memory

33. Why the processors are faster??
• A question from computer architecture…..
• https://slideplayer.com/slide/7567250/

34. ASIC Design Styles
• Full Custom IC Design
• Sea-of-Gates (Mask Programmable)
• Gate Arrays (Mask Programmable)
• Embedded Gate Arrays (Mask Programmable)
• Standard Cell Based IC Design
• PLD (PAL-PLA-CPLD)
• FPGA
• Platform/Structured ASIC
• Software Programmable Devices
• Commercial Off-the-Cell (COTS) Devices

35. Full Custom ASIC Design
• The Design flow ( we already learnt!)
Full-custom ICs are the most expensive
to manufacture and to design
Manufacturing lead time (not including design time!) is
typically 8 weeks
• When does it make sense?
there are no suitable existing cell libraries available
existing logic cells are not fast enough
logic cells are not small enough
logic cells consume too much power
ASIC is so specialized that some circuits must be
custom designed
• Trends: fewer and fewer full-custom ICs are being
designed (excluding mixed analog/digital ASICs)

36. Mask Programmable Gate Arrays
• Mapping of designs on to the gates in the array
• Gates are designed, characterized and
prefabricated
• Customized placement and interconnect
• Fabrication of only top-most interconnects
• Lead time is few days to two weeks
• Channelless Gate Array
• Channelled Gate Array
• Structured Gate Array

37. Sea-of-Gates (Channelless Gate Array)

38. SoG
• Channelless gate array (sea-of-gates or SOG)
 there are no predefined areas set aside
for routing between cells
 we customize the contact layer that
defines the connections between metal1 and transistors
 when use area of transistor for routing,
do not make any contacts to the device underneath
• Characteristics
 only some (the top few) mask layers
are customized – the interconnect
 manufacturing lead time is
between 2 days and 2 weeks

39. Channelled Gate Arrays

40. Channelled Gate Arrays….
• Channelled gate array
we leave space between the rows of transistors
for wiring
• Characteristics
only interconnect is customized
the interconnect uses predefined spaces
between rows
manufacturing lead time is between 2 days
and 2 weeks

41. Embedded Gate Array
Structured Gate Array

42. Embedded Gate Array
 combines features of CBIC and MGA
 motivation: MGA has only fixed gate-array base cell;
difficult and inefficient implementation of memory
 we set aside some IC area and dedicate it to a specific
function
(contain different cells, more suitable for building memory
cells, for example, or complete block, such as a
microcontroller)
• Characteristics
 only some (the top few) mask layers
are customized – the interconnect
 custom blocks can be embedded
 manufacturing lead time is
between 2 days and 2 weeks
 problem: embedded function is fixed

43. Standard Cell

44. Standard Cell Based Design
• Cell-Based ASIC (CBIC) uses predesigned cells
(AND, OR gates, multiplexers, flip-flops, ...)
• Standard-cell areas are built of rows of standard
cells
• Standard-cell areas can be used in combination
with larger predesigned cells (microcontrollers, or
even microprocessors), known as megacells

45. Standard Cell Based Design
Cell Based ASIC (CBIC)

46. Standard Cell Design
• If number of metal layers is limited, feedthrough
cells must be used to route across multiple cell
rows

47. Standard Cell Based Design

48. Platform ASICs
• A pre-manufactured device, used to implement a
custom system on a chip (SoC)
• consists of a group of slices offering different gate
ranges, memory, I/O, PLLs and other intellectual
property such as high speed
Serializer/Deserializers (SerDes)
• A slice may be customized through few layers of
metal for a user application.
• Since only a few layers of metal are customized
for any given design, NRE costs are significantly
lower than a cell-based ASIC where a full mask
set is needed.

49. Platform ASIC : example

50. PLD (PAL-PLA-CPLD)

51. Programmable Logic Devices
• PLDs
 standard ICs, available in standard configurations
 sold in high volume to many different customers
 PLDs may be configured or programmed to create
a part customized to specific application
• Characteristics
 no customized mask layers or logic cells
 fast design turnaround
 a single large block of programmable interconnect
 a matrix of logic macrocells that usually consists of
programmable array logic followed by a flip-flop or latch

52. PLDs…..
• Types of PLDs
 PROM: uses metal fuse that can be blown permanently)
 EPROM: used programmable MOS transistors whose
characteristics are altering by applying a high voltage
 PAL – Programmable Array Logic
programmable AND logic array or AND plane,
and fixed OR plane
 PLA – Programmable Logic Array
 programmable AND plane
followed by programmable OR plane
 CPLD
 FPGA
• Depending on how the PLD is programmed
 erasable PLD (EPLD)
 mask-programmed PLD

53. FPGA

54. Comparison of VLSI Implementations
Cost vs Volume

55. Comparison of VLSI Implementations

57. VLSI Design Tools
• By Chip vendor
• By third party
• Cadence
• Mentor Graphics
• Synopsis
• Microwind

59. Coverage of my lectures….
• ASIC
• Full Custom
• CMOS Design
• Simulation
• Layout
• SemiCustom
• Verification
• Gate Array
• Std. Cell
• DFT
• STA
• FP-Floor Plan
• CTC – Clock Tree
Synthesis
• FPGA
• HDL Entry
• Place and Route

60. THANK YOU!
1/24/2019