This document discusses built-in self-test (BIST) techniques for integrated circuits. It provides an overview of BIST architecture, which includes a test pattern generator, test application to the circuit under test, and a response verification component. The document outlines different methods for test pattern generation, such as exhaustive, pseudo-exhaustive, pseudo-random, and test pattern augmentation. It also describes various response compaction techniques like parity testing, one counting, transition counting, and signature analysis that are used to compact the circuit response due to the large amount of test data produced. Benefits of BIST include reduced testing costs and ability to test at operating speeds, while costs include increased chip area and testing of the BIST hardware

1. Built-In-Self-Test
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org

2. Acknowledgement
2
3December
2019
This presentation has been summarized
from various books, papers, websites and
presentations and so on …. all over the
world. I couldn’t remember where these
large pull of hints and work come from.
However, I’d like to thank all professors and
scientists who create such a good work on
this emerging field. Without those efforts in
this very emerging technology, these notes
and slides can’t be finished. I am thankful
to them to make my teaching process more
effective.
DrUshaMehta

3. Why BIST?
• Useful for field test and diagnosis (less expensive than a
local automatic test equipment)
• Software tests for field test and diagnosis:
• Low hardware fault coverage
• Low diagnostic resolution
• Slow to operate
• Hardware BIST benefits:
• Lower system test effort
• As a means of dealing with the cost of TPG.
• As a means of dealing with increasingly larger
volumes of test data.
• As a means of performing at-speed test.
• Improved system maintenance and repair
• Improved component repair
• Better diagnosis at component level
3
3December2019DrUshaMehta

4. Costly Test Problems Alleviated by BIST
• Increasing chip logic-to-pin ratio – harder observability
• Increasingly dense devices and faster clocks
• Increasing test generation and application times
• Increasing size of test vectors stored in ATE
• Expensive ATE needed for GHz clocking chips
• Hard testability insertion – designers unfamiliar
with gate-level logic, since they design at behavioural
level
• Shortage of test engineers
• Circuit testing cannot be easily partitioned
4
3December2019DrUshaMehta

5. • BIST entails three tasks:
• TPG
• Test application
• Response verification
• Types of BIST:
• Memory BIST
• Logic BIST
• Combinations for testing RAM-based FPGAs.
• In this course, we will focus on logic BIST, used for
testing random logic.
5
3December2019DrUshaMehta

6. Benefits of BIST
6
3December2019DrUshaMehta

7. BIST Benefits…..
In general, BIST
• Reduced testing and maintenance cost
• Lower test generation cost
• Reduced storage / maintenance of test patterns
• Simpler and less expensive ATE
• Can test many units in parallel
• Shorter test application times
• Can test at functional system speed
7
3December2019DrUshaMehta

8. BIST Costs…
• Chip area overhead for:
• Test controller
• Hardware pattern generator
• Hardware response compacter
• Testing of BIST hardware
• Pin overhead -- At least 1 pin needed to activate BIST
operation
• Performance overhead – extra path delays due to BIST
• Yield loss – due to increased chip area or more chips In
system because of BIST
• Reliability reduction – due to increased area
• Increased BIST hardware complexity – happens when
• BIST hardware is made testable
8
3December2019DrUshaMehta

9. Overview of BIST Architecture
• Do remember that all components are on-chip in this
case.
9
3December2019DrUshaMehta

10. BIST Architecture
10
3December2019DrUshaMehta

11. Test Generation
• Store in ROM – too expensive
• Exhaustive
• Pseudo-exhaustive
• Pseudo-random (LFSR) – Preferred method
• Binary counters – use more hardware than LFSR
• Modified counters
• Test Pattern Augmentation
• LFSR combined with a few patterns in ROM
•
11
3December2019DrUshaMehta

12. Exhaustive Pattern Generator (Counter)
• Shows that every state and transition works
• For n-input circuits, requires all 2n vectors
• Impractical for large n ( > 20 )
12
3December2019DrUshaMehta

13. Pseudo Exhaustive Pattern Generation
13
3December2019DrUshaMehta

14. Random Pattern Generation
14
3December2019DrUshaMehta

15. Pseudo Random Pattern Generation
• Standard Linear Feedback Shift Register (LFSR)
• Normally known as External XOR type LFSR
• Produces patterns algorithmically – repeatable
• Has most of desirable random properties
• Need not cover all 2n input combinations
• Long sequences needed for good fault coverage
15
3December2019DrUshaMehta

16. Weighted Pseudo Random Pattern
Generation
• LFSR p (1) = 0.5
• Solution:
• Add programmable weight selection and complement LFSR
bits to get p(1)’s other than 0.5
• Need 2-3 weight sets for a typical circuit
• Weighted pattern generator drastically shortens pattern
length for pseudo-random patterns
16
3December2019DrUshaMehta

17. Test Pattern Augmentation
• Secondary ROM – to get LFSR to 100% SAF coverage
• Add a small ROM with missing test patterns
• Add extra circuit mode to Input MUX – shift to ROM
patterns after LFSR done
• Important to compact extra test patterns
• Use diffracter:
• Generates cluster of patterns in neighbourhood of
stored ROM pattern
• Transform LFSR patterns into new vector set
• Put LFSR and transformation hardware in full-scan
chain
17
3December2019DrUshaMehta

18. Response Verification
• The response of the logic-under-test needs to be checked
after test application using test pattern generator ( with
an LFSR!).
• It is difficult to check the response of every pattern
(storage requirements).
• Severe amounts of data in CUT response to LFSR
patterns – example:
• Generate 5 million random patterns
• CUT has 200 outputs
• Leads to: 5 million x 200 = 1 billion bits response
• Uneconomical to store and check all of these responses
on chip
• Responses must be compacted ( not “compressed”) 18
3December2019DrUshaMehta

19. Some Definitions…
• Aliasing – Due to information loss, signatures of good
and some bad machines match
• Compaction – Drastically reduce # bits in original
circuit response – lose information
• Compression – Reduce # bits in original circuit response
– no information loss – fully invertible (can get back
original response)
19
3December2019DrUshaMehta

20. Compaction Testing Techniques
• Parity testing
• One counting
• Transition counting
• Syndrome calculation
• Signature analysis
20
3December2019DrUshaMehta

21. Parity Testing
21
3December2019DrUshaMehta

22. One Counting
22
3December2019DrUshaMehta

23. Transition Counting
23
3December2019DrUshaMehta

24. Signature Analysis
24
3December2019DrUshaMehta

25. BILBO works as both TPG and RC
25
3December2019DrUshaMehta

26. Questions????
Thanks !