Field Programmable Gate Arrays, FPGA

1. 12/8/2023 FPGA Architecture 1
Field Programmable
Gate Arrays
Dr Usha Mehta
usha.mehta@nirmauni.ac.in
08-12-2023
Usha Mehta 1

2. 12/8/2023 FPGA Architecture 2
Acknowledgement
This presentation has been summarized from various
books, papers, websites and presentations related to the
topic all over the world. I couldn’t remember where
these large pull of hints and work come from. However,
I’d like to thank all professors and scientists who
created such a good work on this emerging field.
Without those efforts in this very emerging technology,
these notes and slides can’t be finished.
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3. 12/8/2023 FPGA Architecture 3
How Microprocessor Programming is
different from FPGA Programming?
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4. 12/8/2023 FPGA Architecture 4
Evolution from CPLD
• Approach to building a “better” PLD is place a lot of primitive gates on a
die, and then place programmable interconnect between them:

5. 12/8/2023 FPGA Architecture 5
Evolution
• Around 1980’s, there was a gap in digital ICs
• SPLD-CPLD : Programmable, fast design time,
flexibility in design modification but could not support
complex design
• ASIC : Could support complex design but painfully
expensive in time and cost, once the design has been
implemented, it’s frozen, no flexibility.
• To gap this bridge, Xilinx introduces FPGAs
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6. 12/8/2023 FPGA Architecture 6
Programmability of FPGAs
• Device-wide Programmability
• The way in which device computes can be programmed
• In processor, all programmability is in sequence of
activity, the circuit block itself has fixed functionality
• Where does this programmability come from?
• Programmable Logic Block
• Programmable Input/Output
• Programmable routing/interconnect
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7. 12/8/2023 FPGA Architecture 7
Basics of FPGA
The FPGA approach to arrange primitive logic
elements (logic cells) arrange in rows/columns with
programmable routing between them.
What constitutes a primitive logic element? Lots of
different choices can be made! Primitive element
must be classified as a “complete logic family”.
• A primitive gate like a NAND gate
• A 2/1 mux (this happens to be a complete logic
family)
• A Lookup table (I.e, 16x1 lookup table can
implement any 4 input logic function).
Often combine one of the above with a DFF to form
the primitive logic element.

8. 12/8/2023 FPGA Architecture 8
Comparison of FPGA-ASIC-
Microprocessor
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9. 12/8/2023 FPGA Architecture 9
FPGA’s popularity in applications like…
• Glue Logic (replace SSI and MSI parts)
• Rapid turnaround
• Prototype design
• Emulation
• Custom computing
• Dynamic reconfiguration
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10. 12/8/2023 FPGA Architecture 10
When FPGAs are good choice?
• High speed needed (compared to Microprocessor)
• Computation can be parallelized
• Bit level operations
• Reconfigurability is important
• Small to medium size production quantity
• No strict power constraints ( compared to ASICs)
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11. 12/8/2023 FPGA Architecture 11
Cons of FPGAs
• Power consumption (compared to ASIC)
• Long design time ( compared to microprocessor-
software)
• Silicon Area overhead
• 20 to 80% in ASIC (DFT)
• 90% in Processor (Caches etc)
• 99% in FPGA ( programmable logic and routing)
• No need to worries…. MOORE’S LAW is there….
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12. 12/8/2023 FPGA Architecture 12
FPGA Classification
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Implementation
Architecture
Logic
Implementation
Programmable
Technology
Symmetrical Array
Row based Array
Hierarchial PLD
Sea of Gates
Look Up table
Multiplexer
based
PLD Block
NAND Gates
Static Ram
Antifuse
E/EPROM
FPGA types

13. 12/8/2023 FPGA Architecture 13
SRAM Based FPGA : Xilinx
• Island/Cellular structure
• Volatile
• Required external memory to store
programming info / bit stream file
• Very less power
• Large area
• Easy to reconfigure
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14. 12/8/2023 FPGA Architecture 14
EPROM Based : Altera
• Array based
• Non-volatile
• Reconfigurable ( out of circuit/ In circuit)
• High Power consumption
• Small in size
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15. 12/8/2023 FPGA Architecture 15
Antifuse Based : Actel
• Channeled
• Non volatile
• One time programmable
• Small in size
• Less Power
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16. 12/8/2023 FPGA Architecture 16
Island Style Xilinx FPGA
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CLB
CLB CLB
CLB CLB
CLB
Configurable
Logic
Block
IOB
IOB
IOB IOB IOB
Input
Output
Block
Programmable
Interconnect

17. 12/8/2023 FPGA Architecture 17
SRAM for Xilinx
• Each programmable point is SRAM cell being loaded
from external source.
• This SRAM cells are written only once for each
application so no need of high speed like commercial
SRAM
• The SRAM is volatile but SRAM FPGAs include a logic
to sense power-on and to automatically initialize them
selves and reconfigure the FPGA so providing virtually-
non-volatility provided application can wait 2ms-30ms.
• Hence this FPGAs need an external memory
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18. 12/8/2023 FPGA Architecture 18
5T SRAM Cell from Xilinx
• Being used for every kind of programmability in Xilinx
• Logic block : LUT
• Interconnections
• Input/Output Configurations
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19. 12/8/2023 FPGA Architecture 19
Programmability in
Logic
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20. 12/8/2023 FPGA Architecture 20
:Primitive Gates / Universal Gates
• PAL and PLA use the SOP form and hence use INV,
AND and OR arrays.
• The gate requirements vary with functions.
• Example: For a 4 variable functions, there are 224
possible functions and each require the different no of
AND and OR gates.
• Even if we implement the functions using NAND/ NOR
gates (Universal gates), the requirement of no. of gates
varies with function.
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21. 12/8/2023 FPGA Architecture 21
Multiplexer
• Any Boolean function can be implemented using 2:1
MUX.
• If 8 variable function is to be implemented using single
MUX, what can be the size of MUX?
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22. 12/8/2023 FPGA Architecture 22
Boolean Function using MUX
• For F (x, y, z) = Σ(1,3,5,6)
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23. 12/8/2023 FPGA Architecture 23
Lookup Table
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SRAM

24. 12/8/2023 FPGA Architecture 24
LUT using 2:1 MUX
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25. 12/8/2023 FPGA Architecture 25
Example 2 Input LUT
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x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 1
f = x1'x2' + x1x2, or using Shannon's expansion:
f = x1'(x2') + x1(x2)
= x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))
f
1
0
0
1
x1
x2

26. 12/8/2023 FPGA Architecture 26
3 Input LUT
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– 7 2x1 MUXes and
8 storage cells are
required
– Commercial LUTs have
4-5 inputs, and 16-32
storage cells
f
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x2
x3
x1

27. 12/8/2023 FPGA Architecture 27
LUT using Transmission Gate
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28. 12/8/2023 FPGA Architecture 28
Out
D Q
Clock
Select
Flip-flop
In
1
In
2
In
3
LUT
Se logic block = LUT + Flipflop
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29. 12/8/2023 FPGA Architecture 29
Fine Grained FPGAs
• Fine Grained: Small Unit like NAND gates, LUTs,
MUXes only…..
• When complex building blocks / Units are also present
in CLB, then it is called Coarse Grained FPGA.
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30. 12/8/2023 FPGA Architecture 30
Programmability in
Interconnections
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31. 12/8/2023 FPGA Architecture 31
Routing
• Routing contains 80-90% of FPGA total area
• Mesh based routing network
• Logic blocks are connected to the routing network through
connection
boxes (CB).
• Horizontal and vertical routing tracks which are interconnected
through switch
boxes (SB).
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32. 12/8/2023 FPGA Architecture 32
Routing
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33. 12/8/2023 FPGA Architecture 33
Flexibility in Routing
• FC=Flexibility of Connection
Box
= the number of routing
tracks
of adjacent channel which
are connected to the pin of a
block
• FS=Flexibility of Switch Box
=the total number of tracks
with which every track
entering in the switch box
connects to
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34. 12/8/2023 FPGA Architecture 34
Routing Switch and Connection Switch
• The output pins of a block can connect to any routing
track through pass transistors.
• The pass transistor forms a tristate output that can be
independently turned on or off
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35. 12/8/2023 FPGA Architecture 35
Programmable Interconnect Point (PIP)
Configurable Interconnect Point (CIP)
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36. 12/8/2023 FPGA Architecture 36
Programmable Interconnection Points
PIPs
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36
programmable switch element
turning the corner, etc.

37. 12/8/2023 FPGA Architecture 37
Use of Multiplexer instead of Pass Gate
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38. 12/8/2023 FPGA Architecture 38
Single-Driver Directional Routing
• No use of tristate elements.
• The output of block needs to be connected to the
neighboring routing network through multiplexors in
the switch box.
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39. 12/8/2023 FPGA Architecture 39
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40. 12/8/2023 FPGA Architecture 40
Types of Interconnect
• General Purpose
• Direct Between Adjacent Cell
• Vertical and Horizontal Long Lines
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41. 12/8/2023 FPGA Architecture 41
Short and Long Wire Segments
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42. 12/8/2023 FPGA Architecture 42
Programmability in
Input-Output
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43. 12/8/2023 FPGA Architecture 43
Programmable IOB
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44. 12/8/2023 FPGA Architecture 44
Nomenclature
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45. 12/8/2023 FPGA Architecture 45
Xilinx 3000 Series Logic Cell
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46. 12/8/2023 FPGA Architecture 46
Combinational Logic Options
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47. 12/8/2023 FPGA Architecture 47
Xilinx 3000 Series I/O Block
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48. 12/8/2023 FPGA Architecture 48
Simplified Block Diagram for 4000 Series
CLB
• Two independent function of four variable
• Any one function of five variable
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49. 12/8/2023 FPGA Architecture 49
Realization of Six variable Function –
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50. 12/8/2023 FPGA Architecture 50
Realization of Seven Variable
Function…..
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51. 12/8/2023 FPGA Architecture 51
Fine Grained FPGA
&
Coarse Grained FPGA
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52. 12/8/2023 FPGA Architecture 52
Fine Grained FPGA
• Fine Grained: Small Unit like NAND gates,
LUTs, MUXes only…..
• Gate-Array: regular structure of “logic cells”,
connected through an interconnection
network
• Configuration stored in SRAM, must be
loaded on startup
EPROM

53. 12/8/2023 FPGA Architecture 53
Limitation of Fine Grained FPGA
• If you wanted to do floating point math with a fine
grained LUT2 FPGA, that would not be as efficient and
will have hardware limitations
• What is such complex units are already fabricated in
FPGA as std. cell?
• coarse grained FPGA has floating point, or even
integer, adders, barrel shifters, and or PLA elements in
them that can be cascaded for larger bit words. that
would make a fast adder and take less area than fine
grained and utilize closer to 100% of the complex logic
block.
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54. 12/8/2023 FPGA Architecture 54
Coarse Grained FPGA
• Higher level logic blocks as unit
• Embedded memory
• Many hardware applications need
memory for data storage. Many
FPGAs include blocks of RAM for
this purpose
• Dedicated logic for carry
generation, or other arithmetic
functions
• Phase locked loops for clock
synchronization, division,
multiplication
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I/O Buffer
PLB
Embedded RAM IP Core
Routing

55. 12/8/2023 FPGA Architecture 55
Platform FPGA
• It contains
• CPUs
• Embedded memory
• Memory interface
• High-speed serial I/O standard
• Bus interfaces
• Altera Stratix: Memory blocks + DSP
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56. 12/8/2023 FPGA Architecture 56
Processor in FPGAs
• Softcore microprocessor:
• using FPGA resources only
• Synthesize and compiling need: tools are very important
• Xilinx offering: MicroBlaze & PicoBlaze
• Altera offering: NIOS
• Hardcore microprocessor:
• hardwired in FPGA architecture
• 3rd party tools
• Xilinx: (Virtex II Pro) PowerPC from IBM
• Altera: (Excalibur APEX) ARM922T from ARM
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57. 12/8/2023 FPGA Architecture 57
Soft Core Processor
• Soft-core Processor
• HDL description
• Flexible implementation
• FPGA or ASIC
• Technology independent
• A soft processor is very
configurable
• How to optimize the
implementation without too
many variants?
• Avoid too much low-level and
only do it when necessary
• MicroBlaze is a mixture of
very detailed implementation
and pure RTL code
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HDL
Description
FPGA ASIC
Spartan 3 Virtex 2 Virtex 4

58. 12/8/2023 FPGA Architecture 58
Use of Volatile/Reprogrammability
• At board level test
• As part of test sequence, the FPGA on board is
configured as test generator/checker and after test is
finished, it is reconfigured with regular application
logic.
• Reduces the additional hardware requirement for the
test
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59. 12/8/2023 FPGA Architecture 59
FPGA Soft Core Processors
• Soft Core Processors can have configurable options
• Datapath units
• Cache
• Bus architecture
• Current commercial FPGA Soft-Core Processors
• Xilinx Microblaze
• Altera Nios
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60. 12/8/2023 FPGA Architecture 60
Multi-FPGA System
• Designed for an individual application
• When design is to big or to prototype a new custom
design
• Emulators
• Dynamically reconfigurable systems
• Partitioning and routing is an issue
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61. 12/8/2023 FPGA Architecture 61
Design Flow
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ASIC FPGA

62. 12/8/2023 FPGA Architecture 62
Comparing with ASICs
• The dramatic increase in ASIC design costs have had a real effect on the ASIC
market, reducing the number of new designs and dramatically reducing the
number of vendors serving the ASIC market.
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63. 12/8/2023 FPGA Architecture 63
Does it mean ASIC is over?
• One would expect that such a trend would have a very positive effect on
the FPGA market. This is because there is no mask-set cost associated
with an FPGA design and, accordingly, far lower NRE costs per design.
• “In 2010 there were 2,500 ASIC design starts versus 90,000 FPGA design
starts.” !!!!!!
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64. 12/8/2023 FPGA Architecture 64
Is this reality?
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65. 12/8/2023 FPGA Architecture 65
Current Scenario of Design Starts per
Node
• One can easily see that the most popular current design node is at 180nm.
Clearly, even such an old node provides a better product than the state-of-
the art FPGA. A 65nm Standard Cell design to an FPGA of 28nm suggests
that far more designs could be better off with Standard Cell.

66. 12/8/2023 FPGA Architecture 66

67. 12/8/2023 FPGA Architecture 67
CMOS Logic Market Share
earlier in 2004
Std logic
Programmable
GA
Std cell
Custom
Chipset
Std logic
Programmable
GA
Std cell
Custom
Chipset
Source:dataquest
10%
9%
29%
30%
8%
14%

68. 12/8/2023 FPGA Architecture 68
CMOS PLD Market Share
earlier in 2004
Other
Cpress
AT&T
Actel
Lattice
AMD
Altera
Xilinx
Source:dataquest
5%
3%
5%
6%
11%
15%
24%
31%

69. 12/8/2023 FPGA Architecture 69
Current Scenario of Design Starts per
Node
• One can easily see that the most popular current design node is at 180nm. Clearly,
even such an old node provides a better product than the state-of-the art FPGA.

70. 12/8/2023 FPGA Architecture 70
What stops FPGA to grow drastically?
• A 2007 research paper by Ian Kuon and Prof Jonathan Rose (IEEE Transaction on
Computer-Aided Design of IC and System) says this clearly: "In this paper, we have
presented empirical measurements quantifying the gap between FPGAs and ASICs for
core logic. We found that for circuits implemented purely using the LUT based logic
elements, an FPGA is approximately 35 times larger and between 3.4 to 4.6 times slower
on average than a standard-cell implementation."
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71. 12/8/2023 FPGA Architecture 71
FPGA (Lookup-Table) vs. ASIC (Static
CMOS Gate)
• For CMOS gate, # of transistors depends on
function and # of inputs.
• In SRAM cell, it is fixed. 1 cell requires nearly six
transistors.
• For NAND4 will require 8 transistors. For four
input function in SRAM, 4 X 8 =32 transistors will
be used. In addition to this, it will require
decoder/MUX. How many transistors required for
a mux used to decode the lookup table of 4 bit?
• Delay in CMOS depends on function and # of
inputs but in SRAM, it is always fixed and greater
than CMOS.
• Power in CMOS is only during transition while in
SRAM, it is continuous.
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72. 12/8/2023 FPGA Architecture 72
"Few engineers will design custom chips;
Some engineers will design ASIC and SoCs;
Many engineers will design FPGA systems”
Then how you may differentiate yourself from
those many engineers ?
Of course, by thorough , detailed knowledge of
FPGA starting with PLDs.
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73. 12/8/2023 FPGA Architecture 73
A Maturing Market
• Dominated by two players, Xilinx and Altera
• With 51% and 32% share = 83% combined
• Remaining players scramble for niches
• All non-dedicated players have given up:
• Intel, T.I., Motorola, NSC, AMD, Cypress, Philips…
• Late-comers have been absorbed or failed:
• Dynachip, PlusLogic, Triscend, SiliconSpice (absorbed)
Chameleon, Quicksilver, Morphics, Adaptive Silicon (failed)
The pace of innovation is set by the leaders
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74. 12/8/2023 FPGA Architecture 74
Thank you!
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