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Basic Design Flow for Field Programmable Gate Arrays
The document describes the basic design flow for FPGA development, including selecting a target device, defining system requirements, and major steps in the design process. Key aspects covered are selecting an FPGA with sufficient resources and I/O standards to meet requirements, defining functionality and interfaces in HDL code, simulating and synthesizing the design, and programming the FPGA with a generated bitstream file. Standard FPGA tools are used to implement the design through synthesis, mapping, placement and routing steps.
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Basic Design Flow for Field Programmable Gate Arrays
- 1. Basic Design Flowfor FPGA Usha Mehta usha.mehta@nirmauni.ac.in
- 2. Selection of TargetDevice • Selecting the right device impacts on • Technical feasibility • Schedule • Cost 2 usha mehta 08-12-2023
- 3. Clearly decide SystemRequirements • External Interfaces • PCIe, I2C, SPI4.2, Interlaken etc. • Number of IO Pins • Single ended, differential, Serdes etc. • IO Standards • LVCMOS 2.5V, LVDS, • 3.3V, 2.5V, 1.8V etc. • # of IO pins for each voltage level • Max. frequency • Functionality 3 usha mehta 08-12-2023
- 4. • Hard Macros •Ethernet MAC • PCIe • Serdes • Processors • # of clock pins, PLL, DLL, DCM, clock buffers 4 usha mehta 08-12-2023
- 5. Major Vendors • Xilinx,Altera, Lattice, Actel, Silicon blue etc. • Study the device Product Table from vendors and considering your requirement, select the device. • Tips: • Keep the room for future expansion and bug fixes • Keep the utilization under 80% 5 usha mehta 08-12-2023
- 6. Target Device Which Programmablelogic device? • SPLD, CPLD or FPGA? • When more FFs are required FPGA is a better choice. • It is better to decide before you start your implementation • The selected device is then called the target device 6 usha mehta 08-12-2023
- 7. Basic Design Flow forProgrammable Logic 1. Define the design requirements 2. Describe the design in HDL “THINK THE SAME WAY AS SYNTHESIS TOOL THINKS” 3./4. Simulate the source code 4./3. Synthesis, Optimize and fit the design 5. Download the bit stream file on target device. ( PL. never dump on device or never burnt your device) 7 usha mehta 08-12-2023
- 8.
- 9. Specifications • Define • Specificfunctionality • Inputs, Outputs • Target Device • Speed • Area 9 usha mehta 08-12-2023
- 10. Standard FPGA DesignFlow • Design Entry • Synthesis • Design abstracted as a list of operations and dependencies • Transformed into state diagrams and then logic networks (netlist) • Design Implementation • Translate – merges multiple design files into a single netlist • Map – groups logical components from netlist into IOBs and CLBs • Place & Route – place components on the FPGA and connect them • Device File Programming • Generates a bitstream containing CLB/IOB configuration and routing information to be directly loaded onto the FPGA CprE 583 – Reconfigurable Computing October 4, 2007
- 11. FPGA Design Flow(Xilinx) CprE 583 – Reconfigurable Computing October 4, 2007 Design Entry Synthesis Implementation Device Programming Functional Simulation Timing Simulation HDL files, schematics EDIF/XNF netlist NGD Xilinx primitives file FPGA bitstream
- 12. Design Flow withTest CprE 583 – Reconfigurable Computing October 4, 2007 Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end RC5_core; Specification Verilog description Functional simulation Post-synthesis simulation Synthesized Circuit
- 13. Design Flow withTest (cont.) CprE 583 – Reconfigurable Computing October 4, 2007 Implementation Configuration Timing simulation On chip testing Post-synthesis simulation Synthesized Circuit
- 14. Specifications • Define • Specificfunctionality • Inputs, Outputs • Target Device • Speed • Area 14 usha mehta 08-12-2023
- 15. Design Entry • BlockDiagram/Schematic Capture • State Diagram Entry • HDL Code Entry • IP core HDL Coding • Behavioural • Structural • Data Flow • Mixed…. 15 usha mehta 08-12-2023
- 16. Block Diagram /Schematic Capture 16 usha mehta 08-12-2023
- 17. Block Diagram/Schematic Capture •A schematic circuit is literally “drawn” in an appropriate graphical editor • The EDA tool associated with this task is called Schematic Capture Tool • An electrical rule check (ERC) is usually run • The main job of the ERC tool is to check for incorrect electrical connections for example if a VCC pin of an IC is accidentally shorted to ground, then the ERC tool will point out such a discrepancy • For this tool to be effective the IC pins have to be earlier declared as power, ground, input, output, bidirectional etc. • After removing the ERC errors, a netlist is generated by the editor • A netlist is a text file showing the nets i.e. a set of components connected together • It is also possible to generate VHDL/Verilog netlist 17 usha mehta 08-12-2023
- 18. State Diagram Entry •Many designs are most effectively described /designed by state diagram approach. • Effective for sequential designs • The EDA tools provide a graphical interface so that the designer can directly make an entry of the state diagram and generate the netlist. • This method is preferred since it is a fast way of creating the design 18 usha mehta 08-12-2023
- 19. Hardware Description UsingLanguage • A designer can enter his /her design using a hardware description language (HDL) • The HDLs prominent in the industry are “VHDL” and “Verilog” • There are another languages that is recently making ground called as “System C” and “System Verilog” • Being similar to C language gives it an advantage to be more user friendly and comfortable to designers familiar with C • System Verilog provides a unified approach for design , verification etc. • Using the code entry method is the most preferred one since it offers: • Design flexibility • Code re-use • Easy modification • Tighter control over resources • A netlist is again created by compiling the HDL code 19 usha mehta 08-12-2023
- 20. • Add hardware-specificconstructs to existing languages • SystemC • Popular HDL • Verilog, VHDL • Synthesis-oriented HDL • UDL/I ( Unified Design Language for Integrated Circuits) 20 usha mehta 08-12-2023
- 21.