SlideShare a Scribd company logo
Programmable Switches
Dr Usha Mehta
usha.mehta@nirmauni.ac.in
Acknowledgement
This presentation has been summarized from
various books, papers, websites and
presentations related to the topic all over the
world. I couldn’t remember where these large
pull of hints and work come from. However,
I’d like to thank all professors and scientists
who created such a good work on this
emerging field. Without those efforts in this
very emerging technology, these notes and
slides can’t be finished.
2
Usha
Mehta
08-12-2023
Programmable Switches
Programmable switches are used in PLD for
• Connections
• Wire
• Logic
• Input-Output
• Configurations
• Logic Blocks
3
Usha
Mehta
08-12-2023
Ideal Programmable Switch
• An FPLD contains thousands of such
programmable switches.
• Hence the switches should
• Occupy very less area
• Have very low ON resistance and very high
OFF resistance
• Have very less parasitic capacitance
• Easily fabricated in large number with high
reliability
4
Usha
Mehta
08-12-2023
• Programmable switches may be
• Permanent
• One time Programmable
• Non Permanent
• Reprogrammable
5
Usha
Mehta
08-12-2023
Fuse
• One Time Programmable (OTP)
• Initially: SHORT,
• After programming: OPEN
6
Usha
Mehta
08-12-2023
Array Logic by Fuse
7
Usha
Mehta
08-12-2023
Fuse Programming
8
Usha
Mehta
08-12-2023
Fuse Programmed Logic Array
9
Usha
Mehta
08-12-2023
Antifuse Technology
• Opposite to Fuse
• Initially: OPEN
• Programmed by forcing a current through it:
SHORT
• Actel calls it “Programmable Low-Impedance
Circuit Element (PLICE)”
10
Usha
Mehta
08-12-2023
Antifuse Structure
• Two metal layers
sandwich a layer of
non-conductive,
amorphous silicon.
When voltage is
applied to this
middle layer, the
amorphous silicon
is turned into
polysilicon, which
is conductive.
11
Usha
Mehta
08-12-2023
MOS Structure of Antifuse
12
Usha
Mehta
08-12-2023
ACTEL’s PLICE Structure
13
Usha
Mehta
08-12-2023
Antifuse: Advantages-Disadvantages
• Advantages
• Very small in size hence allows denser switch
population
• Low series resistance
• Low parasitic capacitance
• Disadvantages
• One time programmable
• Requires extra circuitry to deliver the high
programming voltage
• Requires a specific process ( not same as
normal standard integrated circuit process)
14
Usha
Mehta
08-12-2023
Static RAM Programmable Switch
• Use SRAM Cell to control pass transistor or
multiplexer by the bit-content in the SRAM
cell.
15
Usha
Mehta
08-12-2023
SRAM Cell
16
Usha
Mehta
08-12-2023
• Disadvantages
• Volatile
• External Permanent memory required
• Large Area Required
• Advantages
• Easily and quickly reprogrammable
• Requires only standard integrated circuit
process technology for fabrication. No special
requirements like Antifuse
17
Usha
Mehta
08-12-2023
EPROM Technology
• Use of Erasable Programmable Transistor as
switch
• It is an array of floating-gate transistors
individually programmed by an electronic
device that supplies higher voltages than
those normally used in digital circuits.
18
Usha
Mehta
08-12-2023
EPROM Structure
• A FET with floating gate
• The floating gate has no connections to other parts of
the integrated circuit and is completely insulated by
the surrounding layers of oxide
• Storing data requires applying a higher voltage to the
transistors.
• This creates an avalanche discharge of electrons,
which have enough energy to pass through the
insulating oxide layer and accumulate on the gate
electrode.
• When the high voltage is removed, the electrons are
trapped on the electrode.
• Because of the high insulation value of the silicon
oxide surrounding the gate, the stored charge cannot
readily leak away and the data can be retained for
decades. 19
Usha
Mehta
08-12-2023
EPROM as switch
• Become Open path
when programmed
because of the
electrons trapped
on floating gate
raise the threshold
voltage of n
Channel EPROM
above VDD
• Erasable/Reprogra
mmable by
applying UV light
20
Usha
Mehta
08-12-2023
NOR based Flash Memory
21
Usha
Mehta
08-12-2023
Comparison of Switching Technologies
SRAM Antifuse EPROM EEPROM
Manufacturi
ng Process
Easy Hard Hard Hard
Reprogramm
able?
Yes
(in circuit)
No Yes
(Out of
Circuit)
Yes
(in circuit)
Size Large (12X) Small (1X) Small Small
ON
Resistance
600-800
Ohm
100-500
Ohm
1-4K 1-4K
OFF
capacitance
(fF)
10-50 1-3 10-50 10-50
Power
Consumptio
n
Very less less High High
Volatile? Yes No No No
22
Usha
Mehta
08-12-2023
Switching in FPGA
23
Usha
Mehta
08-12-2023
Market Use of Programmable Switches
• Actel: Antifuse
• Xilinx: SRAM
• Altera: EEPROM/FLASH
24
Usha
Mehta
08-12-2023
Radiation Immunity of Programmable
Switches
Antifuse SRAM FLASH
Configuration has been
designated as hard regarding
SEEs.
Configuration has been
designated as the most
susceptible portion of
circuitry.
Configuration
has been
designated as
hard (but NOT
immune)
regarding SEEs
No need of mitigation Strong need of
mitigation
No need of mitigation
08-12-2023
Usha
Mehta
25
Thank you!
26
Usha
Mehta
08-12-2023

More Related Content

What's hot

7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf
Usha Mehta
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design
Usha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehta
Usha Mehta
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis
Usha Mehta
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
Usha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi design
Usha Mehta
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design
Usha Mehta
 
6 verification tools
6 verification tools6 verification tools
6 verification tools
Usha Mehta
 
5 verification methods
5 verification methods5 verification methods
5 verification methods
Usha Mehta
 
Study of inter and intra chip variations
Study of inter and intra chip variationsStudy of inter and intra chip variations
Study of inter and intra chip variations
Rajesh M
 
Testing and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionTesting and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : Introduction
Usha Mehta
 
Static_Time_Analysis.pptx
Static_Time_Analysis.pptxStatic_Time_Analysis.pptx
Static_Time_Analysis.pptx
Ahmed Abdelazeem
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planning
Usha Mehta
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
Usha Mehta
 
Basic synthesis flow and commands in digital VLSI
Basic synthesis flow and commands in digital VLSIBasic synthesis flow and commands in digital VLSI
Basic synthesis flow and commands in digital VLSI
Surya Raj
 
Clock Tree Synthesis.pdf
Clock Tree Synthesis.pdfClock Tree Synthesis.pdf
Clock Tree Synthesis.pdf
Ahmed Abdelazeem
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
shaik sharief
 
Powerplanning
PowerplanningPowerplanning
Powerplanning
VLSI SYSTEM Design
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testing
Usha Mehta
 
PowerPlanning.pdf
PowerPlanning.pdfPowerPlanning.pdf
PowerPlanning.pdf
Ahmed Abdelazeem
 

What's hot (20)

7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehta
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi design
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design
 
6 verification tools
6 verification tools6 verification tools
6 verification tools
 
5 verification methods
5 verification methods5 verification methods
5 verification methods
 
Study of inter and intra chip variations
Study of inter and intra chip variationsStudy of inter and intra chip variations
Study of inter and intra chip variations
 
Testing and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionTesting and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : Introduction
 
Static_Time_Analysis.pptx
Static_Time_Analysis.pptxStatic_Time_Analysis.pptx
Static_Time_Analysis.pptx
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planning
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
 
Basic synthesis flow and commands in digital VLSI
Basic synthesis flow and commands in digital VLSIBasic synthesis flow and commands in digital VLSI
Basic synthesis flow and commands in digital VLSI
 
Clock Tree Synthesis.pdf
Clock Tree Synthesis.pdfClock Tree Synthesis.pdf
Clock Tree Synthesis.pdf
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
 
Powerplanning
PowerplanningPowerplanning
Powerplanning
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testing
 
PowerPlanning.pdf
PowerPlanning.pdfPowerPlanning.pdf
PowerPlanning.pdf
 

Similar to Programmable Switches for Programmable Logic Devices

Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001
BeimarHerediaSaigua1
 
5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU
Raritan
 
Residential wiring PPT.pptx
Residential wiring PPT.pptxResidential wiring PPT.pptx
Residential wiring PPT.pptx
vlkumashankardeekshi th
 
bluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinhabluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinha
Shubham Sinha
 
ELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKERELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKER
ganeshbehera6
 
Circuit bending presentation
Circuit bending presentationCircuit bending presentation
Circuit bending presentation
Dan Wilson
 
Presentation smart city presentation by cs electric (4)
Presentation smart city presentation  by cs electric (4)Presentation smart city presentation  by cs electric (4)
Presentation smart city presentation by cs electric (4)
Mahesh Chandra Manav
 
Installation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plantsInstallation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plants
Gomathy Sengottaiyan
 
energy-harvesting-pres-final-std
energy-harvesting-pres-final-stdenergy-harvesting-pres-final-std
energy-harvesting-pres-final-stdDaniele Costarella
 
Campus networks best practices core and edges network
Campus networks best practices core and edges networkCampus networks best practices core and edges network
Campus networks best practices core and edges network
Ashish Thomas
 
KL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdfKL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdf
SysteDesig
 
Fuses_Lec_1.pptx
Fuses_Lec_1.pptxFuses_Lec_1.pptx
Fuses_Lec_1.pptx
ssuser0531b9
 
Individual project
Individual projectIndividual project
Individual project
Minu Pradeep
 
Clap switch
  Clap switch   Clap switch
Clap switch
OmWakade
 
VLSI Power Reduction
VLSI Power ReductionVLSI Power Reduction
VLSI Power Reduction
Mahesh Dananjaya
 
THE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptxTHE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptx
Ardiansyah58870
 
Single core and multi core cables
Single core and multi core cablesSingle core and multi core cables
Single core and multi core cables
Dr.Raja Masood Larik
 
SoC Power Reduction
SoC Power ReductionSoC Power Reduction
SoC Power Reduction
Mahesh Dananjaya
 
Printed circuit board
Printed circuit boardPrinted circuit board
Printed circuit board
Suhail Ahmed
 

Similar to Programmable Switches for Programmable Logic Devices (20)

Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001
 
5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU
 
Residential wiring PPT.pptx
Residential wiring PPT.pptxResidential wiring PPT.pptx
Residential wiring PPT.pptx
 
bluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinhabluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinha
 
ELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKERELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKER
 
Circuit bending presentation
Circuit bending presentationCircuit bending presentation
Circuit bending presentation
 
Presentation smart city presentation by cs electric (4)
Presentation smart city presentation  by cs electric (4)Presentation smart city presentation  by cs electric (4)
Presentation smart city presentation by cs electric (4)
 
Installation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plantsInstallation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plants
 
energy-harvesting-pres-final-std
energy-harvesting-pres-final-stdenergy-harvesting-pres-final-std
energy-harvesting-pres-final-std
 
Campus networks best practices core and edges network
Campus networks best practices core and edges networkCampus networks best practices core and edges network
Campus networks best practices core and edges network
 
KL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdfKL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdf
 
Wiring a ring main
Wiring a ring mainWiring a ring main
Wiring a ring main
 
Fuses_Lec_1.pptx
Fuses_Lec_1.pptxFuses_Lec_1.pptx
Fuses_Lec_1.pptx
 
Individual project
Individual projectIndividual project
Individual project
 
Clap switch
  Clap switch   Clap switch
Clap switch
 
VLSI Power Reduction
VLSI Power ReductionVLSI Power Reduction
VLSI Power Reduction
 
THE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptxTHE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptx
 
Single core and multi core cables
Single core and multi core cablesSingle core and multi core cables
Single core and multi core cables
 
SoC Power Reduction
SoC Power ReductionSoC Power Reduction
SoC Power Reduction
 
Printed circuit board
Printed circuit boardPrinted circuit board
Printed circuit board
 

More from Usha Mehta

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate Arrays
Usha Mehta
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf
Usha Mehta
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf
Usha Mehta
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memory
Usha Mehta
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yield
Usha Mehta
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
Usha Mehta
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_design
Usha Mehta
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI Design
Usha Mehta
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)
Usha Mehta
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)
Usha Mehta
 

More from Usha Mehta (10)

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate Arrays
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memory
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yield
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_design
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI Design
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)
 

Recently uploaded

DESIGN A COTTON SEED SEPARATION MACHINE.docx
DESIGN A COTTON SEED SEPARATION MACHINE.docxDESIGN A COTTON SEED SEPARATION MACHINE.docx
DESIGN A COTTON SEED SEPARATION MACHINE.docx
FluxPrime1
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
Divya Somashekar
 
road safety engineering r s e unit 3.pdf
road safety engineering  r s e unit 3.pdfroad safety engineering  r s e unit 3.pdf
road safety engineering r s e unit 3.pdf
VENKATESHvenky89705
 
ML for identifying fraud using open blockchain data.pptx
ML for identifying fraud using open blockchain data.pptxML for identifying fraud using open blockchain data.pptx
ML for identifying fraud using open blockchain data.pptx
Vijay Dialani, PhD
 
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
MdTanvirMahtab2
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Teleport Manpower Consultant
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
Massimo Talia
 
Railway Signalling Principles Edition 3.pdf
Railway Signalling Principles Edition 3.pdfRailway Signalling Principles Edition 3.pdf
Railway Signalling Principles Edition 3.pdf
TeeVichai
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
BrazilAccount1
 
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdfAKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
SamSarthak3
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
AmarGB2
 
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&BDesign and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Sreedhar Chowdam
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
karthi keyan
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
Osamah Alsalih
 
HYDROPOWER - Hydroelectric power generation
HYDROPOWER - Hydroelectric power generationHYDROPOWER - Hydroelectric power generation
HYDROPOWER - Hydroelectric power generation
Robbie Edward Sayers
 
space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
ongomchris
 
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
zwunae
 
Hierarchical Digital Twin of a Naval Power System
Hierarchical Digital Twin of a Naval Power SystemHierarchical Digital Twin of a Naval Power System
Hierarchical Digital Twin of a Naval Power System
Kerry Sado
 

Recently uploaded (20)

DESIGN A COTTON SEED SEPARATION MACHINE.docx
DESIGN A COTTON SEED SEPARATION MACHINE.docxDESIGN A COTTON SEED SEPARATION MACHINE.docx
DESIGN A COTTON SEED SEPARATION MACHINE.docx
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
 
road safety engineering r s e unit 3.pdf
road safety engineering  r s e unit 3.pdfroad safety engineering  r s e unit 3.pdf
road safety engineering r s e unit 3.pdf
 
ML for identifying fraud using open blockchain data.pptx
ML for identifying fraud using open blockchain data.pptxML for identifying fraud using open blockchain data.pptx
ML for identifying fraud using open blockchain data.pptx
 
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
 
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
 
Railway Signalling Principles Edition 3.pdf
Railway Signalling Principles Edition 3.pdfRailway Signalling Principles Edition 3.pdf
Railway Signalling Principles Edition 3.pdf
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
 
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdfAKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
 
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&BDesign and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
 
HYDROPOWER - Hydroelectric power generation
HYDROPOWER - Hydroelectric power generationHYDROPOWER - Hydroelectric power generation
HYDROPOWER - Hydroelectric power generation
 
space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
 
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
一比一原版(IIT毕业证)伊利诺伊理工大学毕业证成绩单专业办理
 
Hierarchical Digital Twin of a Naval Power System
Hierarchical Digital Twin of a Naval Power SystemHierarchical Digital Twin of a Naval Power System
Hierarchical Digital Twin of a Naval Power System
 

Programmable Switches for Programmable Logic Devices

  • 1. Programmable Switches Dr Usha Mehta usha.mehta@nirmauni.ac.in
  • 2. Acknowledgement This presentation has been summarized from various books, papers, websites and presentations related to the topic all over the world. I couldn’t remember where these large pull of hints and work come from. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Usha Mehta 08-12-2023
  • 3. Programmable Switches Programmable switches are used in PLD for • Connections • Wire • Logic • Input-Output • Configurations • Logic Blocks 3 Usha Mehta 08-12-2023
  • 4. Ideal Programmable Switch • An FPLD contains thousands of such programmable switches. • Hence the switches should • Occupy very less area • Have very low ON resistance and very high OFF resistance • Have very less parasitic capacitance • Easily fabricated in large number with high reliability 4 Usha Mehta 08-12-2023
  • 5. • Programmable switches may be • Permanent • One time Programmable • Non Permanent • Reprogrammable 5 Usha Mehta 08-12-2023
  • 6. Fuse • One Time Programmable (OTP) • Initially: SHORT, • After programming: OPEN 6 Usha Mehta 08-12-2023
  • 7. Array Logic by Fuse 7 Usha Mehta 08-12-2023
  • 9. Fuse Programmed Logic Array 9 Usha Mehta 08-12-2023
  • 10. Antifuse Technology • Opposite to Fuse • Initially: OPEN • Programmed by forcing a current through it: SHORT • Actel calls it “Programmable Low-Impedance Circuit Element (PLICE)” 10 Usha Mehta 08-12-2023
  • 11. Antifuse Structure • Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive. 11 Usha Mehta 08-12-2023
  • 12. MOS Structure of Antifuse 12 Usha Mehta 08-12-2023
  • 14. Antifuse: Advantages-Disadvantages • Advantages • Very small in size hence allows denser switch population • Low series resistance • Low parasitic capacitance • Disadvantages • One time programmable • Requires extra circuitry to deliver the high programming voltage • Requires a specific process ( not same as normal standard integrated circuit process) 14 Usha Mehta 08-12-2023
  • 15. Static RAM Programmable Switch • Use SRAM Cell to control pass transistor or multiplexer by the bit-content in the SRAM cell. 15 Usha Mehta 08-12-2023
  • 17. • Disadvantages • Volatile • External Permanent memory required • Large Area Required • Advantages • Easily and quickly reprogrammable • Requires only standard integrated circuit process technology for fabrication. No special requirements like Antifuse 17 Usha Mehta 08-12-2023
  • 18. EPROM Technology • Use of Erasable Programmable Transistor as switch • It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. 18 Usha Mehta 08-12-2023
  • 19. EPROM Structure • A FET with floating gate • The floating gate has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide • Storing data requires applying a higher voltage to the transistors. • This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. • When the high voltage is removed, the electrons are trapped on the electrode. • Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. 19 Usha Mehta 08-12-2023
  • 20. EPROM as switch • Become Open path when programmed because of the electrons trapped on floating gate raise the threshold voltage of n Channel EPROM above VDD • Erasable/Reprogra mmable by applying UV light 20 Usha Mehta 08-12-2023
  • 21. NOR based Flash Memory 21 Usha Mehta 08-12-2023
  • 22. Comparison of Switching Technologies SRAM Antifuse EPROM EEPROM Manufacturi ng Process Easy Hard Hard Hard Reprogramm able? Yes (in circuit) No Yes (Out of Circuit) Yes (in circuit) Size Large (12X) Small (1X) Small Small ON Resistance 600-800 Ohm 100-500 Ohm 1-4K 1-4K OFF capacitance (fF) 10-50 1-3 10-50 10-50 Power Consumptio n Very less less High High Volatile? Yes No No No 22 Usha Mehta 08-12-2023
  • 24. Market Use of Programmable Switches • Actel: Antifuse • Xilinx: SRAM • Altera: EEPROM/FLASH 24 Usha Mehta 08-12-2023
  • 25. Radiation Immunity of Programmable Switches Antifuse SRAM FLASH Configuration has been designated as hard regarding SEEs. Configuration has been designated as the most susceptible portion of circuitry. Configuration has been designated as hard (but NOT immune) regarding SEEs No need of mitigation Strong need of mitigation No need of mitigation 08-12-2023 Usha Mehta 25