This document summarizes and compares different domino circuit designs for wide fan-in OR gates. It describes 8 different domino circuit techniques: 1) Standard Footless Domino, 2) Conditional-Keeper Domino, 3) High-Speed Domino, 4) Leakage Current Replica Keeper Domino, 5) Controlled Keeper by Current-Comparison Domino, 6) Diode Footed Domino, 7) Diode-Partitioned Domino, and 8) Wide Fan-In OR gate Current Comparison Domino. It simulates these circuits in 180nm, 130nm, and 90nm technologies and compares their power, propagation delay, energy, and energy-delay product performance.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An integrated high power-factor converter with zvs transitionLeMeniz Infotech
An integrated high power-factor converter with zvs transition
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of >200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
In this paper a review of the dynamic logic circuit design has been done as these circuits are used due to their high performance, high speed and less number of transistors in the circuit. The number of required transistors is lesser than the CMOS logic style. The OR dynamic logic style is not applicable as it has low noise tolerance at the dynamic stage which can change the output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and has less capacitance at the output node.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Ultra Low Power Design and High Speed Design of Domino Logic CircuitIJERA Editor
The tremendous success of the low-power designs of VLSI circuits over the past 50 years has significant change
in our life style. Integrated circuits are everywhere from computers to automobiles, from cell phones to home
appliances. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or
NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and
extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less
resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which
increases performance compared to existing domino logic styles. According to the simulations in cadence
virtuoso 65nm CMOS process, the proposed circuit shows the improvement of up thirty percent compared
existing domino logics.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An integrated high power-factor converter with zvs transitionLeMeniz Infotech
An integrated high power-factor converter with zvs transition
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of >200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
In this paper a review of the dynamic logic circuit design has been done as these circuits are used due to their high performance, high speed and less number of transistors in the circuit. The number of required transistors is lesser than the CMOS logic style. The OR dynamic logic style is not applicable as it has low noise tolerance at the dynamic stage which can change the output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and has less capacitance at the output node.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Ultra Low Power Design and High Speed Design of Domino Logic CircuitIJERA Editor
The tremendous success of the low-power designs of VLSI circuits over the past 50 years has significant change
in our life style. Integrated circuits are everywhere from computers to automobiles, from cell phones to home
appliances. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or
NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and
extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less
resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which
increases performance compared to existing domino logic styles. According to the simulations in cadence
virtuoso 65nm CMOS process, the proposed circuit shows the improvement of up thirty percent compared
existing domino logics.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino LogicIDES Editor
Dynamic logic style is used in high performance
circuit design because of its fast speed and less transistors
requirement as compared to CMOS logic style. But it is not
widely accepted for all types of circuit implementations due
to its less noise tolerance and charge sharing problems. A
small noise at the input of the dynamic logic can change the
desired output. Domino logic uses one static CMOS inverter
at the output of dynamic node which is more noise immune
and consuming very less power as compared to other proposed
circuit. In this paper we have proposed a novel circuit for
domino logic which has less noise at the output node and has
very less power-delay product (PDP) as compared to previous
reported articles. Low PDP is achieved by using semi-dynamic
logic buffer and also reducing leakage current when PDN is
not conducting. This paper also analyses the PDP of the circuit
at very low voltage and different W/L ratio of the transistors.
Design of complex arithmetic logic circuits considering ground noise, leakage current, active power and area is a challenging task in VLSI circuits. In this paper, a comparative analysis of high performance power gating schemes is done which minimizes the leakage power and provides a way to control the ground noise. The innovative power gating schemes such as stacking power gating , diode based stacking power gating are analyzed which minimizes the peak of ground noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 80% over the conventional power gating. It is also found that in stacking power gating, the ground noise has been reduced by a small extent over the conventional power gating scheme. We have performed simulations using Tanner in a 180nm standard CMOS technology at room temperature with supply voltage of 2.5 V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective road map for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Similar to Iaetsd design and analysis of low-leakage high-speed (20)
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
#vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore#blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #blackmagicforlove #blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #Amilbabainuk #amilbabainspain #amilbabaindubai #Amilbabainnorway #amilbabainkrachi #amilbabainlahore #amilbabaingujranwalan #amilbabainislamabad
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Iaetsd design and analysis of low-leakage high-speed
1. 1
Design and Analysis of Low-Leakage High-Speed
Domino Circuit for Wide Fan-In OR Gates.
M.Chennakeshavulu1, K.Subramanyam2
1Associate Professor, ECE, RGMCET, JNTUA, Nandyal, A.P, India
1Onlinechenna@yahoo.com
2M.Tech Student, ECE, RGMCET, JNTUA, Nandyal, A.P, India
2Subbuking987@gmail.com
Abstract--Domino CMOS logic circuit relations finds a
broad variety of applications in microprocessors, digital
signal processors, and dynamic memory owing to their
high speed and low device count. In this paper a new
domino circuit is studied, which has a lower leakage and
higher noise immunity, lacking dramatic speed
degradation for wide fan-in gates. The system which is
utilized in this paper is based on comparison of Power,
Propagation Delay, Energy, and Energy Delay
Propagation. The studied circuit technique decreases
the parasitic capacitance on the dynamic node, yielding
a smaller keeper for wide fan-in gates for the fast and
robust circuits. Thus, the disputation current and
consequently power consumption and delay are
reduced. The leakage current is also decreased by
exploiting the footer transistor in diode configuration,
which results in increased noise immunity. This the
studied technique is applying in 90nm, 130nm, and
180nm technology using TANNER tools.
Index Terms: Domino logic,leakage-tolerant, noise
immunity and wide fan-in.
I.INTRODUCTION
CMOS gates are mostly designed using static logic
and dynamic logic. DYNAMIC logic such as domino
logic is widely used in lots of applications to get high
performance, which cannot be get with static logic
styles [1].But, the major drawback of dynamic logic
families is that they are more sensitive to noise than
static logic families. When the technology scales down,
the supply voltage is reduced for low power, and the
threshold voltage (Vth) is also scaled down to reach
high performance. while reducing the threshold voltage
exponentially increases the subthreshold leakage
current, drop of leakage current and improving noise
immunity are of main concern in robust and high-
performance designs in recent technology generations,
especially for wide fan-in dynamic gates [2], robustness
and performance significantly degrade with increasing
leakage current.
Fig. 1. Standard Footless Domino circuit.
As a result, it is complex to get satisfactory robustness–
performance tradeoffs. In this paper comparison-based
domino (CCD) circuits for wide fan-in applications in
ultra deep sub micrometer technologies are studied.
The originality of the studied circuits is concurrently
increases performance and decreases leakage power
consumption. In this paper we are studied High speed
Domino circuits for wide(4,8,16) FAN –IN applications.
The most well-liked dynamic logic is the
conventional standard domino circuit as shown in Fig.
1. In this design, a pMOS keeper transistor is working to
stop any undesired discharging at the dynamic node
due to the leakage currents and charge distribution of
the pull-down network in the evaluation phase .Hence
improving the robustness by using keeper
transistor. The keeper ratio K is defined as
K = (1)
Where W and L denote the transistor size, and μn and
μp are the electron and hole mobilities.Even if the
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
26
2. 2
keeper upsizing improves noise immunity it increases
current contention between the keeper transistor and
the evaluation network. Thus, it increases power
consumption and evaluation delay of standard domino
circuits. These problems are graver in wide fan-in
dynamic gates due to the huge number of leaky nMOS
transistors connected to the dynamic node. Hence, there
is a tradeoff between robustness and performance, and
the number of pull-down legs is limited. The existing
techniques try to compromise one feature to gain at the
expense of the other.
Several circuit techniques are studied. These
circuit techniques can be divided into 2 categories.
In the 1st category, circuit techniques to
modify the controlling circuit of the gate voltage of the
keeper such as
1.Standrad Footless Domino(SFLD)[1],
2. Conditional-Keeper Domino (CKD)[3]
3. High-Speed Domino (HSD) [4],,
4. Leakage Current Replica (LCR) Keeper
Domino [5], &
5. Controlled Keeper by Current-Comparison
Domino (CKCCD) [6].
And the 2nd category, designs including the designs to
vary the circuit topology of the footer transistor in the
evaluation network such as
6. Diode Footed Domino (DFD) [2] and
7. Diode-Partitioned Domino (DPD)[7]
These 2 category techniques are explained in given
bellow.
2. Conditional-Keeper Domino (CKD):
It is one of the standard versions of domino logic as
shown in Fig.2. Here 2 keeper transistors are used. At
the commencement of evaluation phase, the minor
keeper K2 charges the dynamic node in case if all the
inputs are LOW. Then after delay end, if dynamic node
still remains charged, the NAND gate turns the better
keeper transistor ON to stay the dynamic node HIGH for
the rest of evaluation phase. If the dynamic node has
discharged, the keeper transistors remain OFF.
Fig.2 Conditional Keeper Domino [3]
This circuit has a few drawbacks such as decreasing
delay of the inverters and the NAND gate has a few
restrictions. Robustness can be achieved by using the
larger keeper. The increase in size of delay element
improves noise immunity but power dissipation and
delay increases.
3. High-Speed Domino (HSD) :
Here delay is introduced in clock by using two inverters
as shown in Fig.3, in arrange to reduce the current
during the PMOS keeper at the initial of evaluation
phase which leads to reduce the power dissipation up to
some extent. This makes it probable to use physically
powerful keeper without performance degradation and
improve the noise margin. Other than the power and
area overhead of clock delay circuit remains. In pre-
charge phase, when clock becomes LOW, transistor Mp1
turns ON and dynamic node is charged to logic HIGH
and in the start of evaluation phase, Mp2 still turns ON
which keeps the keeper transistor Mk to OFF condition.
After delay completion Mp2 turns OFF.
Fig.3 High speed Domino (HSD)[3]
In connecting this, the inputs make the logic function
as well as in case if input(s) are logic HIGH then
provides discharge path for dynamic node and output
changes to logic HIGH and Mk is in OFF condition as a
logic high as (VDD-Vtn) voltage, where Vtn is NMOS
threshold voltage, is passed to Mk which does not turn
it into ON state. And if no input is HIGH then dynamic
node is not discharged and output is still LOW. So Mn1
turns ON and pass logic LOW to Mk which turns it ON
and dynamic node is kept at logic HIGH. In this way,
keeper transistor prevents charge leakage in High speed
domino logic. The difficulty with high speed domino
logic (HSD) is that a voltage of VDD - Vtn is accepted
through the NMOS transistor Mn1 which leads to a
small dc current through the keeper transistor and pull-
down network and also large noise at input terminals of
PDN causes the dynamic node discharge because of no
footer transistor.
4. Leakage Current Replica (LCR) Keeper Dom
In LCR Keeper domino circuit the transistor size is
varied as shown in Fig.4, the mirror transistor M1 is set
to 7Lmin to reduce channel length modulation and
reduce variation of the threshold voltage. The width of
transistor M2 is same to the sum of the widths of the
nMOS transistors of the PDN. The width of the keeper
transistors of the gates, which are simulated using the
LCR keeper, are varied to get the desired delay.
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
27
3. 3
Fig.4 Leakage Current Replica Domino [5]
5. Controlled Keeper by Current-Comparison
Domino (CKCCD):
The reference circuit [12] of the leakage current
consists of transistors M5, M6, M7 and M8. The
transistor M5 is off inactive mode and will be on in
standby mode to decrease standby power. The size of
the mirror transistor M3 is selected based on the
leakage of the pull down transistors. The mirror current
should be greater than the pull down leakage and minor
than the lowest PDN discharge, current with at least one
in put at the high logic level to make sure correct
operation. Since the reference circuit is a replica circuit
of the PDN, the reference current varied switch
temperature presently similar to the PDN leakage
current. Thus, the design is almost insensitive to
temperature variations.
Fig.5 Controlled Keeper by Current-Comparison Domino[6]
6. Diode Footed Domino (DFD):
Diode-footed domino [12] is reduced leakage current,
enhanced performance and better strength as shown in
fig.6 . In this circuit,M1 is the diode footer, which is in
sequence with the evaluation network. Leakage current
is reduced by M1 due to the stacking effect. Also M1
increases the switching threshold voltage of the gate
and there by improves noise immunity. The mirror
transistor and current feedback improve the robustness
of the circuit against sub-threshold leakage and input
noise in the deep submicron range.
Fig6. Diode Footed Domino[2]
7. Diode-Partitioned Domino (DPD):
In the DPD according to [7] each partition Consists of 4
legs to get the most excellent results as shown in fig.7.
All inverters and keepers of the partitions are set to
least size and the length of the major keeper transistor
MK . The desired delay is achieved by varying the size
of the precharge and keeper transistors.
Fig.7 Diode-Partitioned Domino
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
28
4. 4
8.Wide FAN-IN or gate Current comparision comparision Domino:
This circuit is similar to a replica leakage circuit [7], in which a series diode-connection transistor M6 similar to M1 is
added. In fact, as shown in Fig.8,.The circuit has five extra transistors and a shared reference circuit compared to standard
footless domino (SFLD).
Fig 8.Wide FAN-IN or gate Current comparision
comparision Domino
The circuit can be well thought-out as two stages. The
first stage reevaluation network includes the PUN and
transistors MPre,MEval, and M1.The PUN.The second
stage looks like a footless domino with one input [node
A in fig5],without any charge sharing, one transistor M2
regardless of the Boolean function in the PUN,and a
controlled keeper consists of two transistors. Only one
pull-up transistor is connected to the dynamic node
instead of the n-transistor in the n-bit OR gate to
decrease capacitance on the dynamic node, yielding a
higher speed. The input signal of the second stage is
prepared by the first stage. In the evaluation phase,
thus, the dynamic power consumption consists of two
parts: one part for the first stage and the other for the
second stage.
A. Predischarge Phase:
Input signals and clock voltage are in high and low
levels, correspondingly, [CLK = “0”, CLK = “1” in Fig.8] in
this phase. Then, the voltages of the dynamic node
(Dyn) and node A have fallen to the low level by
transistor MDis and raised to the high level by
transistor Mpre, in that order. Hence, transistors Mpre,
MDis, Mk1, and Mk2 are on and transistors M1, M2, and
MEval are off. Also, the output voltage is raised to the
high level by the output inverter.
B. Evaluation Phase:
In this phase, clock voltage is in the high level [CLK =
“1”, CLK = “0” in Fig. 8] and input signals can be in the
low level. Therefore, transistors Mpre and MDis are off,
transistor M1, M2, Mk2, and MEval are on, and
transistor Mk1 can become on or off depending on input
voltages. Thus, two states may occur. First, all of the
input signals remain high. Second, at least one input
falls to the low level. In the first state, a little amount of
voltage is established across transistor M1 due to the
leakage current. Even if this leakage current is mirrored
by transistor M2, the keeper transistors of the second
stage (Mk1 and Mk2) compensate this mirrored leakage
current. It is obvious that upsizing the transistor M1 and
increasing the mirror ratio (M) increase the speed due
to higher mirrored current at the expense of noise-
immunity degradation. In the second state, when at
least one conduction path exists, the pull-up current
flow is raised and the voltage of node A is decreased to
nonzero voltage, which is equal to gate-source voltage
of the saturated transistor M1.
9. SIMULATION RESULTS AND COMPARISONS
These circuits are simulated using TANNER Tools
TSPICE in the high-performance 180 nm, 130nm, and
90nm predictive technology. The supply voltage used in
the simulations is 2 V in the wide fan-in (4, 8, 16, input)
OR-gate,circuit.The simulated dynamic circuits results
of Power,Delay,Energy,Energy Delay Propagation as
shown in given tables
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
29
5. 5
TABLE-I
Comparisons of power, delay, energy, E.D.P of SFLD Wide FAN-IN Gates(4,8,16 in puts)
IN
PUTS
180nm 130nm 90nm
4 in
Averag
e
Power
Propaga
tion
Delay
Energy E.D.P Averag
e
Power
Propaga
tion
Delay
Energy E.D.P A.P P.D Ener
gy
E.D.P
3.5x
10
-4
w
31ns 10.8x
10
-13
3363.5
x10-22
4.7x
10-4
w
31ns 145.7x
10-13
4516x
10-22
6x
10-4
w
30n 36x
10-13
1080x
10-22
8 in
3.43X
10-4
w
31n 106x
10-13
3296x
10-22
4.59x
10-4
w
31n 142.2x
10-13
4410x
10-22
6.38x
10-4
w
30n 191x
10-13
5742x
10-22
16in
3.52X
10-4
w
31n 109x
10-13
3382x
10-22
4.6x
10-4
w
31n 142.6x
10-13
4420x
10-22
6.69x
10-4
w
31n 207x
10-13
6429x
10-22
TABLE-II
Comparisons of power, delay, energy, E.D.P of CKD Wide FAN-IN Gates (4, 8, 16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propag
ation
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
1.34X
10-4
w
31n 41.5x
10-13
1287x
10-22
1.6x
10-3
w
31n 49.6x
10-12
1537x
10-21
9.6x
10-3
w
30n 288x
10-12
8640x
10-21
8 in 1.3X
10-3
w
30n 39x
10-12
1170x
10-21
1.67x
10-3
w
30n 50.1x
10-12
1503x
10-22
6.38x
10-4
w
30n 191x
10-13
5742x
10-22
16
in
1.17X
10-3
w
31n 36.2x
10-12
1124x
10-21
1.53x
10-3
w
31n 47.4x
10-12
1470x
10-21
2.13x
10-3
w
30n 63.9x
10-12
1917x
10-21
TABLE-III
Comparisons of power, delay, energy, E.D.P of HSD Wide FAN-IN Gates (4, 8, 16 in puts)
IN
PUT
180nm 130nm 90nm
4in
Average
Power
Propaga
tion
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
3.6x
10-4
w
31n 111.6x
10-13
3459x
10-22
4.65x
10-4
w
31n 144x
10-13
4468x
10-22
6.5x
10-4
w
30
n
195x
10-13
5850x
10-22
8in 3.59X
10-4
w
31n 111x
10-13
3449x
10-22
4.69x
10-4
w
31n 145.3x
10-13
4507x
10-22
6.5x
10-4
w
30
n
195x
10-13
5850x
10-22
16in 3.65X
10-4
w
31n 113x
10-13
3507x
10-22
4.73x
10-4
w
31n 146.6x
10-13
4545x
10-22
6.77x
10-4
w
30
n
203x
10-13
6093x
10-22
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
30
6. 6
TABLE-IV
Comparisons of power, delay, energy, E.D.P of LCR Keeper Wide FAN-IN Gates (4, 8, 16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propaga
tion
Delay
Energy E.D.P Average
Power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
3.51x
10-4
w
31n 108x
10-13
3373x
10-22
4.5x
10-4
w
31n 139x
10-13
4309x
10-22
6.37x
10-4
w
30
n
191x
10-13
5733x
10-22
8 in 3.52X
10-4
w
31n 109x
10-13
3382x
10-22
4.60x
10-4
w
31n 142.6
x
10-13
4420x
10-22
6.37x
10-4
w
30
n
191x
10-13
5733x
10-22
16 in 3.57X
10-4
w
31n 110x
10-13
3430x
10-22
4.64x
10-4
w
31n 143.8
x
10-13
4459x
10-22
6.62x
10-4
w
31
n
205x
10-13
6361x
10-22
TABLE-V
Comparisons of power, delay, energy, E.D.P of CKCCD Wide FAN-IN Gates (4, 8, 16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propag
ation
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
2.3x
10-4
w
30n 69x
10-13
2070x
10-22
3.2x
10-4
w
31n 99.2x
10-13
3075x
10-22
6.06x
10-4
w
30n 181x
10-13
5454x
10-22
8 in 2.41X
10-4
w
31n 74.7x
10-13
2316x
10-22
3.19x
10-4
w
31n 98.89
x
10-13
3065x
10-22
3065
x
10-22
31n 114x
10-13
3536x
10-22
16 in 2.46X
10-4
w
31n 76.2x
10-13
2364x
10-22
3.2x
10-4
w
31n 99.2x
10-13
3075x
10-22
3.7x
10-4
w
31n 114x
10-13
3555x
10-22
TABLE-VI
Comparisons of power, delay, energy, E.D.P of DFD Wide FAN-IN Gates (4, 8, 16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propag
ation
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
3.54X
10-4
w
30n 106x
10-13
3186x
10-22
4.71x
10-4
w
30n 141.1x
10-13
4239x
10-22
6.07x
10-4
w
30
n
182x
10-13
5463x
10-22
8 in 3.67X
10-4
w
31n 113x
10-13
3526x
10-22
4.79x
10-4
w
31n 148.4x
10-13
4603x
10-22
5.84x
10-4
w
30
n
175x
10-13
5256x
10-22
16 in 3.71X
10-4
w
31n 115x
10-13
3565x
10-22
4.86x
10-4
w
31n 150.5x
10-13
4670x
10-22
6.02x
10-4
w
30
n
180x
10-13
5400x
10-22
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
31
7. 7
TABLE-VII
Comparisons of power, delay, energy, E.D.P of DPD Wide FAN-IN Gates(4,8,16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propag
ation
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
3.70X
10-4
w
30n 111x
10-13
3330x
10-22
6.12x
10-4
w
30n 183.6x
10-13
5508x
10-22
6.16x
10-4
w
30
n
184x
10-13
5544x
10-22
8 in 3.67X
10-4
w
31n 113x
10-13
3526x
10-22
4.79x
10-4
w
31n 148.4x
10-13
4603x
10-22
5.84x
10-4
w
30
n
175x
10-13
5256x
10-22
16 in 3.66X
10-4
w
31n 113x
10-13
3517x
10-22
6.42x
10-4
w
30n 192.6x
10-13
5778x
10-22
6.0x
10-4
w
30
n
180x
10-13
5400x
10-22
TABLE-VIII
Comparisons of power, delay, energy, E.D.P of CCD Wide FAN-IN Gates (4,8,16 in puts)
IN
PUT
180nm 130nm 90nm
4 in
Average
Power
Propag
ation
Delay
Energy E.D.P Average
power
Propaga
tion
Delay
Energy E.D.P A.P P.D Energy E.D.P
1.07X
10-4
w
1.53
n
1.63x
10-13
2.50x
10-22
2.25x
10-4
w
0.9n 20.25x
10-13
18.2x
10-22
4.19x
10-4
w
0.3
n
1.25x
10-13
0.3771x
10-22
8 in 8.34X
10-4
w
1.29
n
10.7x
10-13
13.8x
10-22
1.39x
10-4
w
1.3n 1.807x
10-13
2.34x
10-22
2.3x
10-4
w
0.1
n
0.23x
10-13
0.023x
10-22
16 in 0.92X
10-4
w
12n 132x
10-22
132x
10-22
1.57x
10-4
w
1.19
n
1.86x
10-13
2.22x
10-22
2.5x
10-4
w
83
n
207x
10-13
1722x
10-22
Fig.9. Comparison of power supply with same delay
10. CONCLUSION:
The leakage current of the evaluation network of
dynamic gates was considerably increased with
technology scaling, particularly in wide domino gates,
yielding reduced noise immunity and improved power
consumption. So, new designs were required to get
preferred noise robustness in wide fan-in circuits. Also,
rising the fan-in not only reduced the worst case delay.
The main aim is to make the domino circuits extra
robust and with low leakage without significant
performance degradation or increased power
consumption. This was done by comparing the
evaluation current of the gate with the leakage current.
Keeper size of very high fan-in gates. Using the high-
performance 180 nm [3] at a power supply of 2 V, wide
0
1
2
3
4
SFLD CKD HSD LCR keeper CKCCD DFD DPD CCD
4 in
8 in
16 in
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
32
8. 8
fan-in 4 to 16-bit OR gate circuit. The proposed design
plus several existing circuit designs were simulated and
compared, imulation results verified significant
progress in leakage reduction and satisfactory speed for
high-speed applications. moreover, they verified that.
Thus, the CCD was above all suitable for implementing
wide fan-in Boolean logic functions with high noise
immunity, lower area consumption, time delay, Energy,
Energy, Delay Propagation and power consumption.
Moreover, a normalized FOM, previously proposed by
the authors, was modified to include standard deviation
of delay.
REFERENCES:
[1] J. M. Rabaey, A. Chandrakasan, and B. Nicolic, Digital
Integrated Circuits: A Design Perspective, 2nd ed. Upper
Saddle River, NJ:Prentice-Hall, 2003.
[2] H. Mahmoodi and K. Roy, “Diode-footed domino: A
leakage-tolerant high fan-in dynamic circuit design
style,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no.
3, pp. 495–503, Mar. 2004.
[3] Sumit Sharma “ A Novell High-speed low-power
domino logic technique for static output in evaluation
phase for high frequency inputs” IJERA march 2014..
[4] M. H. Anis, M. W. Allam, and M. I. Elmasry, “Energy-
efficient noise-tolerant dynamic styles for scaled-down
CMOS and MTCMOS technologies,” IEEE Trans. Very
Large Scale (VLSI) Syst., vol. 10, no. 2, pp. 71–78, Apr.
2002.
[5] Y. Lih, N. Tzartzanis, and W. W. Walker, “A leakage
current replica keeper for dynamic circuits,” IEEE J.
Solid-State Circuits, vol. 42, no. 1,pp. 48–55, Jan. 2007.
[6] A. Peiravi and M. Asyaei, “Robust low leakage
controlled keeper by current-comparison domino for
wide fan-in gates, integration,” VLSI J., vol. 45, no. 1, pp.
22–32, 2012.
[7] H. Suzuki, C. H. Kim, and K. Roy, “Fast tag
comparator using diode partitioned domino for 64-bit
microprocessors,” IEEE Trans. Circuits Syst., vol. 54, no.
2, pp. 322–328, Feb. 2007.
[8] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-
Meimand, “Leakage current mechanisms and leakage
reduction techniques in deep sub micrometer CMOS
circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327,Feb.
2003.
[9] N. Shanbhag, K. Soumyanath, and S. Martin, “Reliable
low-power design in the presence of deep submicron
noise,” in Proc. ISLPED, 2000, pp. 295–302.
[10] M. Alioto, G. Palumbo, and M. Pennisi,
“Understanding the effect of process variations on the
delay of static and domino logic,” IEEE Trans. Very Large
Scale (VLSI) Syst., vol. 18, no. 5, pp. 697–710, May 2010.
[11] H. Mostafa, M. Anis, and M. Elmasry, “Novel timing
yield improvement circuits for high-performance low-
power wide fan-in dynamic OR gates,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 58, no. 10, pp. 1785–
1797, Aug. 2011.
[12] Ali Peiravi , Mohammad Asyaei “Current-
Comparison-Based Domino: New Low-Leakage High-
Speed Domino Circuit for Wide Fan-In Gates” VOL. 21,
NO. 5, MAY 2013
M.CHENNAKESAVALU, He completed
B.Tech in 2003 at JNTUHyderabadand He completed
M.Tech in 2010 at JNTUAnantapur.He got lecturership
in UGCNET-2013.He has 10 years of teaching
experience. He is working as ASSOC.professor in Dept of
ECE, in RGMCET,Nandyal. He published Nearly12
papers in Various publication. His research areas are
low power VLSI design and interconnects in NOC.He has
professional memberships in MIETE. He guided 5
projects at master level.
K.SUBRAMANYAM received the B.E
degree in electronics and communications engineering
from the JNT University of Anantapur in 2008 to 2012.
He is currently pursuing the M.E. degree in digital
systems and computer electronics engineering from the
JNT University of Anantapur. His current research
interests include low-power, high-performance, and
robust circuit design for deep-sub micrometer CMOS
technologies.
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
33
![1
Design and Analysis of Low-Leakage High-Speed
Domino Circuit for Wide Fan-In OR Gates.
M.Chennakeshavulu1, K.Subramanyam2
1Associate Professor, ECE, RGMCET, JNTUA, Nandyal, A.P, India
1Onlinechenna@yahoo.com
2M.Tech Student, ECE, RGMCET, JNTUA, Nandyal, A.P, India
2Subbuking987@gmail.com
Abstract--Domino CMOS logic circuit relations finds a
broad variety of applications in microprocessors, digital
signal processors, and dynamic memory owing to their
high speed and low device count. In this paper a new
domino circuit is studied, which has a lower leakage and
higher noise immunity, lacking dramatic speed
degradation for wide fan-in gates. The system which is
utilized in this paper is based on comparison of Power,
Propagation Delay, Energy, and Energy Delay
Propagation. The studied circuit technique decreases
the parasitic capacitance on the dynamic node, yielding
a smaller keeper for wide fan-in gates for the fast and
robust circuits. Thus, the disputation current and
consequently power consumption and delay are
reduced. The leakage current is also decreased by
exploiting the footer transistor in diode configuration,
which results in increased noise immunity. This the
studied technique is applying in 90nm, 130nm, and
180nm technology using TANNER tools.
Index Terms: Domino logic,leakage-tolerant, noise
immunity and wide fan-in.
I.INTRODUCTION
CMOS gates are mostly designed using static logic
and dynamic logic. DYNAMIC logic such as domino
logic is widely used in lots of applications to get high
performance, which cannot be get with static logic
styles [1].But, the major drawback of dynamic logic
families is that they are more sensitive to noise than
static logic families. When the technology scales down,
the supply voltage is reduced for low power, and the
threshold voltage (Vth) is also scaled down to reach
high performance. while reducing the threshold voltage
exponentially increases the subthreshold leakage
current, drop of leakage current and improving noise
immunity are of main concern in robust and high-
performance designs in recent technology generations,
especially for wide fan-in dynamic gates [2], robustness
and performance significantly degrade with increasing
leakage current.
Fig. 1. Standard Footless Domino circuit.
As a result, it is complex to get satisfactory robustness–
performance tradeoffs. In this paper comparison-based
domino (CCD) circuits for wide fan-in applications in
ultra deep sub micrometer technologies are studied.
The originality of the studied circuits is concurrently
increases performance and decreases leakage power
consumption. In this paper we are studied High speed
Domino circuits for wide(4,8,16) FAN –IN applications.
The most well-liked dynamic logic is the
conventional standard domino circuit as shown in Fig.
1. In this design, a pMOS keeper transistor is working to
stop any undesired discharging at the dynamic node
due to the leakage currents and charge distribution of
the pull-down network in the evaluation phase .Hence
improving the robustness by using keeper
transistor. The keeper ratio K is defined as
K = (1)
Where W and L denote the transistor size, and μn and
μp are the electron and hole mobilities.Even if the
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
26](https://image.slidesharecdn.com/iaetsd-designandanalysisoflow-leakagehigh-speed-150407214114-conversion-gate01/85/Iaetsd-design-and-analysis-of-low-leakage-high-speed-1-320.jpg)
![2
keeper upsizing improves noise immunity it increases
current contention between the keeper transistor and
the evaluation network. Thus, it increases power
consumption and evaluation delay of standard domino
circuits. These problems are graver in wide fan-in
dynamic gates due to the huge number of leaky nMOS
transistors connected to the dynamic node. Hence, there
is a tradeoff between robustness and performance, and
the number of pull-down legs is limited. The existing
techniques try to compromise one feature to gain at the
expense of the other.
Several circuit techniques are studied. These
circuit techniques can be divided into 2 categories.
In the 1st category, circuit techniques to
modify the controlling circuit of the gate voltage of the
keeper such as
1.Standrad Footless Domino(SFLD)[1],
2. Conditional-Keeper Domino (CKD)[3]
3. High-Speed Domino (HSD) [4],,
4. Leakage Current Replica (LCR) Keeper
Domino [5], &
5. Controlled Keeper by Current-Comparison
Domino (CKCCD) [6].
And the 2nd category, designs including the designs to
vary the circuit topology of the footer transistor in the
evaluation network such as
6. Diode Footed Domino (DFD) [2] and
7. Diode-Partitioned Domino (DPD)[7]
These 2 category techniques are explained in given
bellow.
2. Conditional-Keeper Domino (CKD):
It is one of the standard versions of domino logic as
shown in Fig.2. Here 2 keeper transistors are used. At
the commencement of evaluation phase, the minor
keeper K2 charges the dynamic node in case if all the
inputs are LOW. Then after delay end, if dynamic node
still remains charged, the NAND gate turns the better
keeper transistor ON to stay the dynamic node HIGH for
the rest of evaluation phase. If the dynamic node has
discharged, the keeper transistors remain OFF.
Fig.2 Conditional Keeper Domino [3]
This circuit has a few drawbacks such as decreasing
delay of the inverters and the NAND gate has a few
restrictions. Robustness can be achieved by using the
larger keeper. The increase in size of delay element
improves noise immunity but power dissipation and
delay increases.
3. High-Speed Domino (HSD) :
Here delay is introduced in clock by using two inverters
as shown in Fig.3, in arrange to reduce the current
during the PMOS keeper at the initial of evaluation
phase which leads to reduce the power dissipation up to
some extent. This makes it probable to use physically
powerful keeper without performance degradation and
improve the noise margin. Other than the power and
area overhead of clock delay circuit remains. In pre-
charge phase, when clock becomes LOW, transistor Mp1
turns ON and dynamic node is charged to logic HIGH
and in the start of evaluation phase, Mp2 still turns ON
which keeps the keeper transistor Mk to OFF condition.
After delay completion Mp2 turns OFF.
Fig.3 High speed Domino (HSD)[3]
In connecting this, the inputs make the logic function
as well as in case if input(s) are logic HIGH then
provides discharge path for dynamic node and output
changes to logic HIGH and Mk is in OFF condition as a
logic high as (VDD-Vtn) voltage, where Vtn is NMOS
threshold voltage, is passed to Mk which does not turn
it into ON state. And if no input is HIGH then dynamic
node is not discharged and output is still LOW. So Mn1
turns ON and pass logic LOW to Mk which turns it ON
and dynamic node is kept at logic HIGH. In this way,
keeper transistor prevents charge leakage in High speed
domino logic. The difficulty with high speed domino
logic (HSD) is that a voltage of VDD - Vtn is accepted
through the NMOS transistor Mn1 which leads to a
small dc current through the keeper transistor and pull-
down network and also large noise at input terminals of
PDN causes the dynamic node discharge because of no
footer transistor.
4. Leakage Current Replica (LCR) Keeper Dom
In LCR Keeper domino circuit the transistor size is
varied as shown in Fig.4, the mirror transistor M1 is set
to 7Lmin to reduce channel length modulation and
reduce variation of the threshold voltage. The width of
transistor M2 is same to the sum of the widths of the
nMOS transistors of the PDN. The width of the keeper
transistors of the gates, which are simulated using the
LCR keeper, are varied to get the desired delay.
INTERNATIONAL ASSOCIATION OF ENGINEERING & TECHNOLOGY
International Conference on Advancements in Engineering Research
ISBN NO : 378 - 26 - 138420 - 8
www.iaetsd.in
27](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)