October 8, 2014 Webcast Identifying PCI Express 3.0 Dynamic Equalization Problems Dynamic equalization training is a unique capability in modern day serial data communication. Through optimization of transmitter and receiver equalization parameters we can push the limits of serial data rates. Troubleshooting dynamic equalization problems at the Physical and Protocol layers requires testing for proper functionality and compliance. Join Teledyne LeCroy's Stephen Mueller for this webinar to understand how to address this measurement challenge. The presentation will include real measurement examples and debugging techniques to pinpoint problems in the physical and protocol layers.

1. Identifying PCIe3.0 Dynamic Equalization Problems
Stephen Mueller –Field Applications Engineer
Stephen.Mueller@teledynelecroy.com

2. PCI Express 3.0 –What’s new?
PCI Express 2.0
PCI Express 3.0
Bit Rate
5 Gb/s
8 Gb/s
Encoding
8B/10B
128B/130B
Overhead
20%
1.5625%
Effective Bit Rate
4 Gb/s per lane
7.88 Gb/s per lane
TransmissionPath
Same as Gen 1
Same as Gen 1 and 2
Receiver Testing
Informative
Required
Link Equalization Testing
NA
Required

3. PCI Express 3.0 PHY Layer
IC System Board PCIE Connector Plug-In Card IC
Signal degrades over long transmission path and connectors

4. How does PCI Express 3.0 Work
TxEQ
RxEQ
TxEQ –De-emphasis and Pre-shoot
RxEQ -CTLE
RxEQ –DFE

5. De-emphasis
No Emphasis
De-emphasis
TxEQ
RxEQ

6. De-emphasis Simulation
TxEQ
RxEQ

7. Copyright © 2012, PCI-SIG, All Rights Reserved
7
Presets and Cursors

8. How does PCI Express 3.0 Work
TxEQ
RxEQ

Tx implements a FIR based equalization

1 of 11 presets are used during TxEQ process

Equalization is based on 3 tap (pre cursor + post cursor) to create de-emphasis and pre-shoot

Rx implements a behavior equalization algorithm

BehavorialCTLE

Behavioral DFE

Behavioral CDR
Rx will send TxEQ preset requests to Tx to optimize TxEQachieving Dynamic Equalizationthrough link initialization

9. LTSSM Walk-Through

10. Dynamic Equalization Phases

There are 4 steps in the equalization process:

Phase 0: Upstream sends Downstream Transmitter and Receiver presets at 2.5G to be used upon entering 8.0G

Phase 1: 8GT/s link established at E-4 BER or better; Both sides advertise EQ capabilities via FS/LF fields

Phase 2: Downstream component adjusts Upstream TX while adjusting its own RX until achieving optimal settings

Phase 3: Upstream component adjusts Downstream TX while adjusting its own RX until achieving optimal settings

Both Preset and Cursor values can be used to adjust TX Equalization settings

There are 10 Presets (pre-defined combinations of de-emphasis and pre- shoot) legal for request during Phase 0, 2, and 3

There are a minimum of 42 combinations of de-emphasis and pre-shoot available when requesting via Cursor values

11. Phase 2
System
Add-in Card
Protocol

12. Phase 2
System
Add-in Card
Protocol
Message sent from root complex (system) to end point (add-in card)
Message sent from end point (add in card) to root complex(system)

13. Phase 2
System
Add-in Card
Protocol

14. Phase 2
System
Add-in Card
Protocol

15. Phase 2
System
Add-in Card
Protocol
The Upstream Port requests specific Transmitter Equalization settings from the Downstream Port by specifying a desired preset or cursor values.

16. Phase 2
System
Add-in Card
Protocol
The Downstream port responds in the protocol confirming it has changed it’s Transmit Equalization settings to the requested preset or cursor value.

17. Channel
Phase 2
System
Add-in Card
Protocol
Electrical
System
Add-in Card
TxEQ
RxEQ

18. Phase 2
System
Add-in Card
Protocol
Electrical
System
Add-in Card
TxEQ
RxEQ
Channel

19. Phase 2
System
Add-in Card
System
Add-in Card
Protocol
Electrical
TxEQ
RxEQ
Channel

20. Phase 2
System
Add-in Card
System
Add-in Card
Protocol
Electrical
TxEQ
RxEQ
Channel

21. Phase 2
System
Add-in Card
Protocol

22. Phase 3
System
Add-in Card
Protocol
Root complex (system) requests preset 1 TxEQsetting from end point (add in card)
End point (add in card) notifies root complex (system) that it’s TxEQhas been set to preset 1

23. What Was Accomplished?
Channel
System
TxEQ
RxEQ
Channel
RxEQ
TxEQ
Channel
Phase 2
Phase 3
System TxEQand Add-in Card RxEQare optimized for the channel
Add-in Card TxEQand System RxEQare optimized for the channel
Result: BER < 10-12
Add-in Card

24. Teledyne LeCroy PCIE Gen3 Line Card
PHY Layer Electrical Transmitter Testing
PHY Layer Electrical
Receiver Testing
LinkEqualization Testing
Scope
Scope+ BERT
Scope + PeRT3 + Protosync
PCI Express® ArchitecturePHY Test Specification Revision 3.0 Section 2.1, 2.2, 2.5, 2.6
PCI Express® ArchitecturePHY Test Specification Revision 3.0 Section 2.9, 2.8PCI Express® Base Specification . Section 4.3
PCI Express® ArchitecturePHY Test Specification Revision 3.0 Section 2.3, 2.4, 2.7, 2.10, 2.11
Built-in 3 tap de-emphasis/pre-shoot and Protocol aware for loopback
initialization and SKP filtering
Only Test Solution in the Industry
for compliance testing and characterization of PCIE Gen3 Link Equalization
Built-in PCIE Gen3 required jitter sources (SJ, RJ, Differential Mode Jitter, Common Mode Jitter)
Proto-Sync PCIE Gen3 decode and trigger for in depth debug and characterization

25. SEG Compliance Testing for PCI-SIG Certification

26. Test Setup

27. Link Equalization with the PeRT

28. 
Trigger

Generator triggers at selected state

Scope captures waveforms (see upper right)

ProtoSync

Waveforms auto-formatted and exported to protocol analyzer software (see lower right)

User “clicking” packets in protocol trace auto-zooms and highlights waveforms in scope window

Analysis

User examines protocol trace and analog waveforms for anomalous data
Protocol and Electrical Data Using Protosync

29. Example: Slow Electrical Response

30. Example: Protocol But No Electrical Response
Everything appears to be working correctly in the protocol
Protocol request for preset 1
Protocol response confirming change to preset 1
Look at the electrical signal and you see the DUT never actually changed to preset 1

31. 
Error: Response to preset/cursor requests must not exceed 500 ns or 1000 ns

Caveat: Late electrical responses won’t be caught by protocol test

Impact: DUT will fail the Link EQ ComplianceTest

Purpose: During link equalization late responses may cause devices to train their receivers improperly
Example: Slow Protocol Response

32. Example: Timeout at Phase 3 Preset Request
PeRT state machine log identifies timeout during dynamic equalization process.
Choose from PeRT trigger list to capture relevant waveform on scope. Splitters are used to pick off the upstream and downstream signal

33. DUT Firmware Bug in EQ Settings
PeRT sends request for Preset 4 –DUT attenuates output to 20mV

34. 
Error: Measured P8 TxEQnot within spec of de-emphasis of 3.5±1.0dB and preshootof 3.5±1.0dB

Caveat: Won’t be caught by protocol test since measurement is electrical

Impact: DUT will fail the Link EQ ComplianceTest

Purpose: Inappropriate P7 or P8 values may result in failure to operate at E-4 or a breakdown in equalization negotiation
Example: Bad TxEQElectrical

35. 
Error: DUT BER not E-12 or better

Impact: DUT will fail the Link EQ ComplianceTest

Purpose: PCIe assumes a low BER. A high BER can cause link to fail and re-train at lower speeds.
Example: BER Exceeds E-12

36. Thank You for Joining Us!
Questions?