Aneesh Raveendran

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I am working in VLSI field. Main areas of work is FPGA and ASIC based system design. Major research areas include :- Computer architecture, Reversible computing Quantum computing Vedic mathematics Network on chip, Application Specific integrated circuit(ASIP) Main focus on research oriented development for INDIA

processor design microprocessor micro controller processor fpga vhdl branch prediction ip core mips computer architecture pipeline stalls pipe lining idealism uart transistors analog design electronic circuits universal asynchronous receive and transmit serial communication rs 232 instruction set control hazard data hazard tcl modelsim reversible logic gates fredkin gate feynman gate not gate toffolli gate reversible computing aligned memory access unaligned memory access memory access external fragmentation internal fragmentation pipe lining superscalar l1 cache arm fpu neon arm cortex-a8 rs232 ieee 802.15.1 protocol system on chip bluetooth on fpga soc bluetooth refcomm alu arithmetic and logic unit fetch module asic decoder execute cisc

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About

Aneesh Raveendran

Presentations

Pipelineing idealisam

Performance Enhancement with Pipelining

Branch prediction

Single_Electron_Transistor_Aneesh_Raveendran

Documents

Design of FPGA based 8-bit RISC Controller IP core using VHDL

Design and Implementation of Bluetooth MAC core with RFCOMM on FPGA

Architecture and Implementation of the ARM Cortex-A8 Microprocessor

Unalligned versus natureally alligned memory access

Reversible Logic Gate

Universal Asynchronous Receive and transmit IP core