Join Teledyne LeCroy for this free webinar as we first cover the basics of a DDR interface with a focus on physical-layer test challenges and solutions to common problems. We will then outline the general procedures and considerations for compliance, debug and validation test scenarios. Finally, case studies will illustrate how to apply sophisticated test tools to solve real-life problems.
Nov 12 Webcast: Eliminate Pitfalls of DDR Memory Testing
Join Teledyne LeCroy's, Mike Hertz, for this free webinar on using an oscilloscope for validation and debug of DDR2/3/4 physical layer measurements.
Topics covered will include: probing, connectivity, recommended device patterns, de-embedding, examples of good and bad waveforms, and debugging steps and techniques.
Mike Hertz has been a Field Applications Engineer with Teledyne LeCroy in Michigan for 14 years.
Highlighted notes while studying Concurrent Data Structures:
DDR4 SDRAM
Source: Wikipedia
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
eMMC 5.0 is the latest generation of embedded NAND Flash IP. Arasan provides a complete solution including digital controllers for host and device, the mixed PHY I/O and pads, software drivers, hardware validation and support.
Nov 12 Webcast: Eliminate Pitfalls of DDR Memory Testing
Join Teledyne LeCroy's, Mike Hertz, for this free webinar on using an oscilloscope for validation and debug of DDR2/3/4 physical layer measurements.
Topics covered will include: probing, connectivity, recommended device patterns, de-embedding, examples of good and bad waveforms, and debugging steps and techniques.
Mike Hertz has been a Field Applications Engineer with Teledyne LeCroy in Michigan for 14 years.
Highlighted notes while studying Concurrent Data Structures:
DDR4 SDRAM
Source: Wikipedia
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
eMMC 5.0 is the latest generation of embedded NAND Flash IP. Arasan provides a complete solution including digital controllers for host and device, the mixed PHY I/O and pads, software drivers, hardware validation and support.
Highlighted notes while studying Concurrent Data Structures:
DDR3 SDRAM
Source: Wikipedia
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
IDT DDR4 RCD register and DB data buffer enable RDIMM and LRDIMM to faster speeds and deeper memories. This video helps you understand the DDR4 feature enhancements of IDT's DDR4 RCD and DB compared to earlier DDR3 technology. An introduction into some available LeCroy testing and debug tools completes the video. Presented by Douglas Malech, Product Marketing Manager at IDT and Mike Micheletti, Product Manager at Teledyne LeCroy. To learn more about IDT's leading portfolio of memory interface products, visit www.idt.com/go/MIP.
Highlighted notes while studying Concurrent Data Structures:
DDR SDRAM
Source: Wikipedia
Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM, and soon will be superseded by DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work in DDR1-equipped motherboards, and vice versa.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
HBM stands for high bandwidth memory and is a type of memory interface used in 3D-stacked DRAM (dynamic random access memory) in GPUs, as well as the server, machine-learning DSP , high-performance computing and networking and client space.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
Fullscreen
Backward Skip 10s
Play Video
Forward Skip 10s
Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Highlighted notes while studying Concurrent Data Structures:
DDR3 SDRAM
Source: Wikipedia
Double Data Rate 3 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR3 SDRAM, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
IDT DDR4 RCD register and DB data buffer enable RDIMM and LRDIMM to faster speeds and deeper memories. This video helps you understand the DDR4 feature enhancements of IDT's DDR4 RCD and DB compared to earlier DDR3 technology. An introduction into some available LeCroy testing and debug tools completes the video. Presented by Douglas Malech, Product Marketing Manager at IDT and Mike Micheletti, Product Manager at Teledyne LeCroy. To learn more about IDT's leading portfolio of memory interface products, visit www.idt.com/go/MIP.
Highlighted notes while studying Concurrent Data Structures:
DDR SDRAM
Source: Wikipedia
Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM, and soon will be superseded by DDR5 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work in DDR1-equipped motherboards, and vice versa.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
HBM stands for high bandwidth memory and is a type of memory interface used in 3D-stacked DRAM (dynamic random access memory) in GPUs, as well as the server, machine-learning DSP , high-performance computing and networking and client space.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
Fullscreen
Backward Skip 10s
Play Video
Forward Skip 10s
Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Get it right the first time lpddr4 validation and compliance testBarbara Aichinger
JEDEC LPDDR4 Compliance and Validation Testing. Learn about electrical and protocol testing and validation. DDR Memory is in almost all computing devices today.
he Associate level of Cisco Certifications can begin directly with CCNA for network installation, operations and troubleshooting or CCDA for network design. Think of the Associate Level as the foundation level of networking certification.
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
In telecommunications, RS-232 is a standard for serial communication transmission of data. It formally defines the signals connecting between a DTE (data terminal equipment) such as a computer terminal, and a DCE (data circuit-terminating equipment, originally defined as data communication equipment[1]), such as a modem. The RS-232 standard is commonly used in computer serial ports. The standard defines the electrical characteristics and timing of signals, the meaning of signals, and the physical size and pinout of connectors. The current version of the standard is TIA-232-F Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange, issued in 1997.
For RF Optimisation and neighbour verification both Scanner and UE measurements are required simultaneously
Post-Processing tool is required for data analysis
Individual call failures or drops can be analysed with Drive test tools (e.g. Nemo Outdoor) but to get bigger picture, a proper analysis tool is required
Actix or Nemo Analyser can be used for
Data analysis
Create Maps
Create KPI reports
Webinar: High Voltage Fiber Optic (HVFO) Probe for Small Signal Floating Meas...teledynelecroy
Join Teledyne LeCroy for this webinar as we provide an overview of the differences between a conventional high-attenuation HV differential probe, a HV isolated oscilloscope input, and the HVFO, along with some real-world measurement examples.
PAM4 Analysis and Measurement Webinar Slidedeckteledynelecroy
In this Teledyne LeCroy webinar we explore the acquisition and analysis of PAM4 waveforms. We will cover PAM4 test configurations, compliance measurements and debug techniques.
There are numerous design challenges associated with implementing Automotive Ethernet. This session will discuss what to test in order to improve the chances of a successful design
The Basics of Automotive Ethernet Webinar Slidedeckteledynelecroy
Evolving from the BroadR-Reach standard, Automotive Ethernet enables faster data communication to meet the demands of today’s vehicles and the connected vehicles of the future.
This session will focus on the fundamentals of the Automotive Ethernet ecosystem. It will include a brief history and evolution of the standard, and an overview of benefits of the new technology and the associated design challenges. We will conclude with an introduction into the test requirements and the analysis tools available to help troubleshoot and qualify designs.
USB 3.1 Gen 2 Compliance Testing and Debug Webinarteledynelecroy
Join Teledyne LeCroy for this free webinar as we analyze the major changes in the standard compared to its previous versions and offer solutions for compliance testing and debug to help in analysis and characterization of USB 3.1 Gen 2 signals and interfaces.
Webinar Slides: Measurements and Analysis for Switched-mode Power Designsteledynelecroy
This webinar covers the measurements of interest for designers of switched-mode power conversion circuits and devices. With the goal of high efficient and reliable designs, we review the acquisition of voltage and current, their relationship in switched-mode power conversion circuits.
We review specific power circuit performance areas including the analysis of power device switching losses, conduction losses, dynamic on-resistance, control loop response, power quality, conducted emissions, best practices for probing power circuits, and power rail integrity measurements.
Webinar Slides: Probing Techniques and Tradeoffs – What to Use and Whyteledynelecroy
Engineers must commonly probe low and high frequency signals with high signal fidelity. Typical passive probes with high input impedance and capacitance provide good response at lower frequencies, but inappropriately load the circuit and distort signals at higher frequencies.
Join Teledyne LeCroy for this webinar as we discuss:
- Selecting the right probing techniques to maximize the accuracy of your measurements
- Probe specifications and their implications on the measured signal
- Variety of probes and accessories available for measurement
- Virtual probing software tools that allow the user to probe the signal when direct access is physically impossible
Webinar Slides: Digital Power Management and Power Integrity Analysis and Tes...teledynelecroy
Join Teledyne LeCroy for an overview of digital power management, power integrity, and power sequencing. We'll discuss test of single or multi-phase digital power management ICs (PMICs), voltage regulator modules (VRMs), point-of-load (POLs) switching regulators, low-dropout (LDO) regulators or other DC-DC converter operations under transient load conditions, and test of complete embedded systems that contain these devices.
Webinar Slides: Probing in Power Electronics - What to use and whyteledynelecroy
Join Teledyne LeCroy for this webinar as we provide an overview of the different HV rated probe specifications and topologies, explain what measurement each probe topology is ideally suited for, and provide real-word examples and comparisons between a variety of different probes and amplifiers.
Join Teledyne LeCroy for a discussion of what S-parameters are and why we should care about them. As serial data rates move into the multi-gigabit domain, S-parameters play an important role in understanding system performance. We will uncover the four main patterns found in s-parameters and learn what they can tell us about our interconnects.
October 8, 2014 Webcast Identifying PCI Express 3.0 Dynamic Equalization Problems
Dynamic equalization training is a unique capability in modern day serial data communication. Through optimization of transmitter and receiver equalization parameters we can push the limits of serial data rates. Troubleshooting dynamic equalization problems at the Physical and Protocol layers requires testing for proper functionality and compliance.
Join Teledyne LeCroy's Stephen Mueller for this webinar to understand how to address this measurement challenge. The presentation will include real measurement examples and debugging techniques to pinpoint problems in the physical and protocol layers.
Essentials of jitter part 3 webinar slidesteledynelecroy
In this final part, we will explore how we measure and analyze jitter in high speed serial links.
We will look at how to take a measurement on less than a million bits and extrapolate the total jitter to a million times as many bits and when we need to find the root cause of jitter, how to decompose the total jitter into its five components.
Essential principles of jitter part 2 the components of jitterteledynelecroy
-The power of statistical analysis
-The five fundamental types of jitter: ISI, DCD, Periodic, Random, Other
-Their statistical “signature”
-The jitter “tree”
-Synthesizing examples based on their root cause
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Webinar: Practical DDR Testing for Compliance, Validation and Debug
1. Practical DDR testing
for compliance, validation and debug
Patrick Connally
patrick.connally@teledyne.com
2. Agenda
Basics of DDR testing
Basics of a DDR interface
Types of testing
Signals of interest
Common DDR test challenges
Signal access
Burst separation
Preparing for physical layer testing
Choosing test equipment
Optimizing oscilloscope setup
DDR compliance testing
Compliance testing background
The compliance testing process
DDR validation and debug
Case study – tracking down a potential
signal fidelity issue
2
4. Basics of a DDR interface
Each DRAM chip
transfers data
to/from the
controller via
several data lines,
accompanied by a
strobe
Since data can
flow both from the
controller to the
DRAM (write
operation) and
from the DRAM to
the controller
(read operation),
these lines are bi-
directional
4
Strobe + Data
DRAM
chip
Controller
5. Basics of a DDR interface
Common clock,
command and
address lines are
used for all DRAM
chips
Since they control
the operation of
the interface, they
are unidirectional
(controller-to-
DRAM)
The layout shown
here is the “fly-by”
topology used
from DDR3
onwards
5
Strobe + Data
Clock, Command, Address
DRAM
chip
Controller
6. Three types of physical-layer test
Compliance: “Do the device’s output signals comply to the JEDEC
specification?”
Validation: “Do the devices interact correctly within the system
environment?”
Debug: “Why isn’t my device/system behaving correctly?”
6
7. Which signals are important?
In physical layer compliance testing
and validation, the fastest signals are
the most critical:
Clock (CK)
Strobe (DQS)
Data (DQn)
These signals need to be analyzed as
analog waveforms to fully
characterize their signal fidelity
While there will be many Data lines in
an interface, testing them all can be
time-consuming
Often, board-level simulation is used to
find the expected “worst-case” data
lines and test only those
7
Strobe
Data
Clock
8. Which signals are important?
The command bus controls the operation of
the interface, and indicates the desired
activity on the high-speed signals
Knowing the logic state of the command bus
signals in a time-correlated way to the analog
behavior of the high-speed CK, DQ and DQS
signals enables much deeper insight into the
system’s behavior
Possible command states vary by DDR
protocol, but can include:
Deselect
No operation
Read
Write
Bank Activate
Precharge
Refresh
Mode Register Set
8
Strobe
Data
CMD bus
9. A complete analysis system
Analog signals
High-bandwidth
oscilloscope
Low-loading
differential
analog probes
9
Analysis software
Identify bursts
Perform
measurement
Digital signals
High-sample-
rate digital
analyzer
High-bandwidth
digital probe
11. Test challenge 1: accessing signal points
All modern DRAM chips are
BGA-packaged, which presents a
challenge for testing – how do
you access signals which are
under the chip?
3 common approaches:
Backside vias
Interposers
DIMM series resistors
11
12. Access option 1: Backside vias
If the BGA balls are accessible on the
back side of the board, this is an ideal
place to probe the signals of interest
Pros
Usually good signal fidelity (probing
near the termination)
Relatively easy access
Cons
Many devices (dual-rank DIMMs,
dense embedded systems) don’t
allow for this method
12
Backside via probe on single-rank DIMM
Backside via probing on “chip-down” system
13. Access option 2: interposers
Interposers install between the DRAM
chip and the board, and provide points
to connect probes
Pros
Useful in difficult access situations
Generally reasonable signal fidelity
Cons
Additional complexity to install
socket correctly
Interposer footprint can cause
problems on crowded boards
13
14. Access option 3: DIMM series resistors
For dual-rank (2-sided) DIMMs, the
backside vias aren’t accessible – the
resistors are a good alternate location
Pros
A relatively accessible probing
point when the vias are not
accessible
Cons
The distance between the probe
and the termination on the DRAM
means reflections from the receiver
can be a problem
14
Single-ended Data line:
resistor to ground
Differential Strobe line
15. Test challenge 2: burst separation
Read and Write bursts share a bus, but must be analyzed separately:
Read bursts originate from the DRAM
Write bursts originate from the controller
Bus is “tri-state” (high-Z at both ends) when neither side is transmitting
It’s critical to be able to identify and isolate the bursts of interest for analysis
15
Idle
Write
Idle
Read
16. Burst separation option 1: DQ/DQS phase
We can use the phase difference
between the Data and Strobe to
differentiate Reads and Writes
Pros
Identification is simple and requires
only the signals being tested
Cons
Signals with lots of noise,
reflections, or slow rise/fall times
can make phase measurements,
and hence burst separation,
unreliable
5/11/2017 18
Write
Read
Clean signals make phase-based separation easy
Reflections can make DQ/DQS phase relationship unclear
17. Burst separation option 2: Command bus
Acquiring or triggering on the
command bus removes any
uncertainty about the coming burst
type
Pros
Very reliable separation
Insight into command bus
activity and relationship to
DQS/DQ
Cons
Requirement to probe several
extra signals
19
19. System bandwidth
Testing DDR systems always
requires the use of probes, so we
should look at the scope and
probes as a complete acquisition
system
DDR interfaces have very fast slew
rates relative to their data transfer
(baud) rates
In order to characterize the system
with acceptable rise-time accuracy,
a relatively high-bandwidth
oscilloscope and probes are
required
21
DDR3 slew rate specification
21. Probe loading
Probe loading gets blamed for a
lot of observed issues
In our experience, signal
fidelity issues can almost
always be traced to the signal
path within the device
Probes with insufficiently low
loading are much more likely to
cause functional failures in
devices
23
Teledyne LeCroy WaveLink
Dxx30 differential probes
have ideal characteristics for
testing higher-rate DDR
systems
22. Probe mechanical connection
Solder-in probe tips are used in the
vast majority of DDR testing
applications
Most critical considerations tend to
be:
Small physical size - typically
many signals need to be probed
Physical flexibility reduces torque
on delicate solder connections
when probe amplifier is moved
Measurement flexibility – doing
several jobs with one tip reduces
test setup complexity
24
Teledyne LeCroy QuickLink
probe tips are low-cost, high
bandwidth, 9-inch flexible tips
that can be interchanged
between analog and digital
instruments
23. Preparing to measure: deskewing
Deskewing is critically important
in all applications where probes
are used for timing
measurements, but even more
so in a DDR environment
The importance of the DQ/DQS
phase in many measurements
makes them particularly
sensitive to skew issues
25
Deskewing probes using the
oscilloscope’s fast edge output
These probing points are close together,
so the same reference plane can be used
24. Preparing to measure: maximize dynamic range
26
Signals are using
~50% of the grid
This reduces Signal-to-Noise
ratio by about 6dB
Signal is “clipping” – it
could be overdriving
the oscilloscope’s
front-end
What not to do.
25. Preparing to measure: maximize dynamic range
5/11/2017 27
Each signal has its
own grid
Maximizes dynamic range
without sacrificing viewability
Each signal occupies
about 6 vertical
divisions
Good practice
26. Preparing to measure: checking signal levels
Make sure the signal levels appear as
specified for the DDR variant you’re
working on
Many automated measurements rely on
“the basics” being correct
If they don’t, it might be…
A probing problem (wrong reference,
cross-probed, inverted)
A device/system problem (Wrong Vdd,
wrong Vref)
28
DDR2 LPDDR2 DDR3 LPDDR3 DDR4 LPDDR4
Vpp
Single-ended 0 to 1.8 V 0 to 1.2 V 0 to 1.5 V 0 to 1.2 V 0 to 1.2 V
Differential -1.8 to 1.8 V -1.2 to 1.2 V -1.5 to 1.5 V -1.2 to 1.2 V -1.2 to 1.2 V
Vref
(reference voltage)
Single-ended 0.9 V 0.6 V 0.75 V 0.6 V 0.6 V
Differential 0 V 0 V 0 V 0 V 0 V
28. Why do compliance testing?
DRAM and/or controller vendors
Must be able to prove to their
customers that their devices abide
by the standards as defined by
JEDEC
There is no formal certification
process for DDR “compliance” –
manufacturers essentially self-certify
This makes documentation of test
procedures and results critical
30
System designers
No explicit need to prove JEDEC
compliance to “downstream”
customers
Validation of device functionality is
much more critical
System layout is often not optimal
for signal fidelity testing
But a compliance report is often
desirable as concrete verification
that design goals have been met
29. Probing for compliance testing
Specification assumes the signal is probed directly at the balls of the
DRAM BGA
This is not always feasible
Access issues
Need to connect twice as many probes
31
CK DQS DQ Add/Ctrl
DDR4 Differential Differential Single-Ended Single-Ended
DDR3 Differential Differential Single-Ended Single-Ended
LPDDR3 Differential Differential Single-Ended Single-Ended
DDR2 Differential Differential or
Single-Ended
Single-Ended Single-Ended
LPDDR2 Differential Differential Single-Ended Single-Ended
30. Compliance testing is complicated!
Fully covering the
JEDEC standard for any
given DDR variant
means doing a lot of
tests.
Automated compliance
test software options for
the oscilloscope…
Make testing less
time-consuming
Reduce errors due
to measurement
complexity
Increase
repeatability
Generate test
reports automatically
32
Test coverage of Teledyne LeCroy QPHY-DDR4 automated compliance test option
31. Step 1: acquire signals
Lots of data
makes for more
reliable,
repeatable results
We take a long
acquisition to
ensure good
statistical
confidence in the
measurements
High traffic density
during testing is
important
Run memtest
or another
script to induce
lots of traffic
33
Clock
Strobe
Data
Address
32. Step 2: separate read/write bursts
Read and Write bursts must be
analyzed separately
They come from different transmitters
Some of their parameters are defined
differently
For systems with high-quality signals
and/or using low speed grades,
DQ/DQS phase produces good
separation results
At higher rates or in low-signal-quality
situations, phase measurement can
become unreliable
In these situations, we recommend
acquiring the CMD bus to ensure
reliable burst separation
34
33. Step 3: perform measurements
35
Measurements are performed on all bursts in the acquired waveform
Results, statistics and screenshots are retained for report generation
Possible reasons for problems/failures:
Signal quality issues due to system/board signal paths
Probes not connected correctly
Burst separation problems (possibly due to the above)
The device does not meet the specification
34. Step 4: Generate eye diagrams
Eye diagrams
are only required
for compliance
testing in DDR4
and LPDDR4
variants
But they are an
incredibly useful
tool for
visualizing
overall signal
quality, so they
form part of the
automated test
package for all
variants
36
36. Step 5: Generate report
Reports contain:
A summary of the test results,
including pass/fail status
More details of each individual
test
Screenshots of the tests being
performed
38
37. DDR Validation and Debug
A case study using Teledyne LeCroy’s DDR Debug Toolkit
39
38. The complete system view
40
Analog probes: DQ/DQS/CK waveforms for
waveshape analysis and eye diagrams
Digital Acquisition: For better burst separation
and insight into command bus behavior
39. What signals are we probing and how?
Strobe (DQS): Analog C2
Data (DQn): Analog C3
Command bus:
Chip Select (CS): Digital D0
Write Enable (WE): Digital D1
Row Address Select (RAS): Digital
D2
Column Address Select (CAS):
Digital D3
Clock (CK): Digital D4 or Analog
C1
QuickLink probe tips can be used
for both digital and analog signals
42
40. Deskew
Make sure to deskew all analog
and digital signals to the same
timing reference
Teledyne LeCroy oscilloscopes
have a Fast Edge output to
make deskewing easy.
43
41. First look at the analog signals
Looking at just
the DQ and
DQS analog
signals, we
can see some
strange non-
monotonicities
on the edges
DDR Debug
Toolkit is the
ideal tool for
tracking down
this kind of
issue
44
43. Bus view
The bus view
also gives a
direct
reference
from the
system
behavior to
the JEDEC
spec
46
44. Look closer with triggers
We can use
the CMD bus
to trigger on
an event of
interest
Let’s trigger
on Read
bursts
They all show
non-
monotonous
edges
47
45. Look closer with triggers
Triggering on
Write bursts
doesn’t show
any evidence
of bad edges
Will the bad
Read edges
affect our
eye
diagrams?
48
46. Eye diagrams and burst separation
The non-
monotonous
edges on the
Read bursts are
hindering the
phase-based
burst separation
approach
It’s hard to
measure
phase with a
discontinuity
right at the
Vref crossing
point
We can see some
Reads end up in
with the Writes as
a result
49
47. Eye diagrams and burst separation
Using the CMD
bus to
separate
Reads and
Writes leads to
“clean” eye
diagrams
But that non-
monotonicity
will cause
problems for
other
measurements
Is it a real
phenomenon?
50
48. Where’s the signal being probed?
5/11/2017 51
PCB
DRAM
Memory
Controller
49. So what’s going on here?
DRAM Controller
Z0 = 50Ω
RT >> 50Ω
VA VB
VA
VB
T1 T2 T3
50. Measure the propagation delay
We can use
the signal
itself as a TDR
pulse
Here, the
round-trip
delay is
approximately
680ps
5/11/2017 53
51. Now we have a simple model
5/11/2017 54
Z0 = 50Ω
RT >> 50Ω
VA VB
TD = 340ps
DRAM Controller
52. This gives us “virtually probed” read bursts
The probing
point has
been “moved”
to the
termination
using Virtual
Probe
technology,
eliminating the
reflections
55
Original Virtual
53. Make sure you pick the correct probe point
5/11/2017 56
PCB
DRAM
Memory
Controller
You should still analyze
Write bursts from here
Read burst analysis
should come from here
“Real” probe Virtual probe
54. The final eye diagram view
When we
view each
signal from
the correct
probing
point, both
Read and
Write bursts
look good
57