This document provides an overview of the PCI Express physical layer technology. It discusses the lane counts and data rates supported by different PCIe versions. It describes the three logical layers of PCIe and divides the physical layer into logical and electrical sub-blocks. It explains several key physical layer technologies including 8b/10b encoding, data scrambling, de-emphasis, and link training. Link training negotiates link parameters and ensures synchronization between devices on the link.

1. Kenyon Tsai
2016.06.22
An overview of PCI Express Physical Layer
Technology

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Introduction

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Introduction
 Lane count : x1, x2, x4, x8, x12, x16 and x32
 Rate :
Raw bit rate Link BW
PCIe 1.x 2.5 Gigabits/s 2 Gb/s
PCIe 2.x 5 Gigabits/s 4 Gb/s
PCIe 3.x 8 Gigabits/s ~8 Gb/s
PCIe 4 16 Gigabits/s ~16 Gb/s

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PCIe Layering Overview
 There are three discrete logical layers
 Transaction Layer
 Data Link Layer
 Physical Layer

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Physical Layer
 The Physical Layer is divided into two blocks
 Logical sub-blocks
 Electrical sub-blocks
Physical Layer
Logical sub-blocks
Electrical sub-blocks

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8b/10b encoding
 Purpose of 8b/10b encoding
 To achieve DC-balance
 Provide enough state changes to allow reasonable clock recovery

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Data Scrambling
 Purposes of scrambling
 For energy dispersal on the carrier
 Reducing inter-carrier signal interference

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De-emphasis
 Definition of De-emphasis

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De-emphasis
 Purposes of De-emphasis
 To compensate Inter-symbol interference

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De-emphasis
 Purposes of De-emphasis
 To compensate Inter-symbol interference

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Link training
 Training Does
 Link data rate negotiation
 Bit lock per Lane
 Lane polarity
 Symbol lock per Lane
 Lane ordering within a Link
 Link width negotiation
 Lane-to-Lane de-skew within a multi-Lane Link

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Link training
 Link Training and Status State Machine (LTSSM) Descriptions

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Link training - Detect
 To detect when a far end termination is present

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