Join Teledyne LeCroy for an overview of digital power management, power integrity, and power sequencing. We'll discuss test of single or multi-phase digital power management ICs (PMICs), voltage regulator modules (VRMs), point-of-load (POLs) switching regulators, low-dropout (LDO) regulators or other DC-DC converter operations under transient load conditions, and test of complete embedded systems that contain these devices.
The document discusses the skin effect phenomenon in conductors carrying alternating current. It defines skin effect as the tendency of AC to flow mostly near the surface of a conductor. It then defines and explains skin depth - the depth at which current density decreases to 1/e of its surface value - and how it depends on frequency, resistivity, and permeability. Factors like eddy currents induced by the changing magnetic field are said to cause the skin effect. The document also provides formulas to calculate skin depth and gives an example using gold at 60 Hz.
Attenuation, distortion, and noise are the main causes of transmission impairments. Attenuation is the reduction of signal strength during transmission, distortion alters the original signal shape, and noise is random electrical interference from internal and external sources that disrupts signal reception. These transmission impairments degrade, weaken, and contaminate signals as they travel through transmission mediums.
This document discusses the design and applications of multicavity klystron amplifiers. It begins by explaining how multicavity klystrons are able to make use of transit time instead of fighting it. It then provides details on the design of multicavity klystrons, including how they contain multiple cavities to improve bunching and efficiency. Finally, it discusses several applications of multicavity klystron amplifiers, including use in UHF-TV transmitters, satellite communication ground stations, radar transmission, and as power oscillators.
Choosing the Segment Length for Adaptive Bitrate StreamingBitmovin Inc
Bitmovin evaluated different segment lengths for adaptive bitrate streaming to determine the optimal length. They found that lengths under 2 seconds performed poorly for encoding efficiency. Lengths of 4 seconds and above had similar performance but shorter lengths hindered streaming performance over HTTP/1.0. Their tests showed 6 second segments performed well over both HTTP/1.0 and HTTP/1.1. Therefore, Bitmovin recommends using variable lengths around 4 seconds on average to balance encoding efficiency and adaptive streaming performance.
The Armstrong method is an indirect method used to generate FM by using a phase modulator. It has two parts:
1. A narrowband FM wave is generated using a phase modulator fed by a crystal oscillator. The stable oscillator allows high frequency stability.
2. Frequency multipliers and a mixer are used to increase the carrier frequency and modulation index of the narrowband FM wave to desired values for broadcast applications. This makes the Armstrong method suitable for broadcast purposes where direct methods using unstable LC oscillators cannot be used.
This document provides an overview of active filters, including their basic types and terminology. The four basic types of active filters are low-pass, high-pass, band-pass, and band-stop (notch) filters. Key terms discussed include poles, order, Butterworth, Chebyshev, and Bessel filters. Circuit configurations for single-pole and two-pole (Sallen-Key) low-pass and high-pass filters are presented.
This document discusses pre-emphasis and de-emphasis in analog communication systems. Pre-emphasis is used at the transmitter to boost higher modulating frequencies, reducing noise effects. It involves passing the audio through a high-pass filter. De-emphasis is used at the receiver to remove the boosting, involving a low-pass filter. Both use time constants of 50 microseconds according to standards. Pre-emphasis increases modulation index for higher frequencies while de-emphasis removes this at the receiver.
Unicast involves sending data from one computer to another, with one sender and one receiver. Multicast sends data to a group of devices that have joined the multicast group, with one sender but multiple potential receivers. Broadcast sends data from one computer that is then forwarded to all connected devices, with one sender and all devices receiving the broadcast traffic.
The document discusses the skin effect phenomenon in conductors carrying alternating current. It defines skin effect as the tendency of AC to flow mostly near the surface of a conductor. It then defines and explains skin depth - the depth at which current density decreases to 1/e of its surface value - and how it depends on frequency, resistivity, and permeability. Factors like eddy currents induced by the changing magnetic field are said to cause the skin effect. The document also provides formulas to calculate skin depth and gives an example using gold at 60 Hz.
Attenuation, distortion, and noise are the main causes of transmission impairments. Attenuation is the reduction of signal strength during transmission, distortion alters the original signal shape, and noise is random electrical interference from internal and external sources that disrupts signal reception. These transmission impairments degrade, weaken, and contaminate signals as they travel through transmission mediums.
This document discusses the design and applications of multicavity klystron amplifiers. It begins by explaining how multicavity klystrons are able to make use of transit time instead of fighting it. It then provides details on the design of multicavity klystrons, including how they contain multiple cavities to improve bunching and efficiency. Finally, it discusses several applications of multicavity klystron amplifiers, including use in UHF-TV transmitters, satellite communication ground stations, radar transmission, and as power oscillators.
Choosing the Segment Length for Adaptive Bitrate StreamingBitmovin Inc
Bitmovin evaluated different segment lengths for adaptive bitrate streaming to determine the optimal length. They found that lengths under 2 seconds performed poorly for encoding efficiency. Lengths of 4 seconds and above had similar performance but shorter lengths hindered streaming performance over HTTP/1.0. Their tests showed 6 second segments performed well over both HTTP/1.0 and HTTP/1.1. Therefore, Bitmovin recommends using variable lengths around 4 seconds on average to balance encoding efficiency and adaptive streaming performance.
The Armstrong method is an indirect method used to generate FM by using a phase modulator. It has two parts:
1. A narrowband FM wave is generated using a phase modulator fed by a crystal oscillator. The stable oscillator allows high frequency stability.
2. Frequency multipliers and a mixer are used to increase the carrier frequency and modulation index of the narrowband FM wave to desired values for broadcast applications. This makes the Armstrong method suitable for broadcast purposes where direct methods using unstable LC oscillators cannot be used.
This document provides an overview of active filters, including their basic types and terminology. The four basic types of active filters are low-pass, high-pass, band-pass, and band-stop (notch) filters. Key terms discussed include poles, order, Butterworth, Chebyshev, and Bessel filters. Circuit configurations for single-pole and two-pole (Sallen-Key) low-pass and high-pass filters are presented.
This document discusses pre-emphasis and de-emphasis in analog communication systems. Pre-emphasis is used at the transmitter to boost higher modulating frequencies, reducing noise effects. It involves passing the audio through a high-pass filter. De-emphasis is used at the receiver to remove the boosting, involving a low-pass filter. Both use time constants of 50 microseconds according to standards. Pre-emphasis increases modulation index for higher frequencies while de-emphasis removes this at the receiver.
Unicast involves sending data from one computer to another, with one sender and one receiver. Multicast sends data to a group of devices that have joined the multicast group, with one sender but multiple potential receivers. Broadcast sends data from one computer that is then forwarded to all connected devices, with one sender and all devices receiving the broadcast traffic.
Transmission line, single and double matchingShankar Gangaju
This document discusses different types of transmission lines used for transmitting energy and signals over long distances. It describes common transmission line media like twisted pair, coaxial cable and optical fiber. It covers their applications in telephone networks, buildings and computer networks. It also discusses their transmission characteristics and limitations. The document compares properties of unshielded and shielded twisted pair. It provides details on utilizing different wavelengths in optical fiber for various applications.
This document discusses peak-to-average power ratio (PAPR) reduction techniques for orthogonal frequency-division multiplexing (OFDM) signals. It begins with an introduction to PAPR and its causes for OFDM signals. It then outlines various PAPR reduction techniques including clipping, coding, probabilistic/scrambling, predistortion, and DFT-spreading. Each technique has benefits but also cons such as distortion, reduced efficiency, or increased complexity. The document provides analysis of PAPR characteristics for different OFDM parameters and modulation schemes.
The dipole and the monopole are arguably the two most widely used antennas across the UHF, VHF and lower-microwave bands. Arrays of dipoles are commonly used as base-station antennas in land-mobile systems. The monopole and its variations are common in portable equipment, such as cellular telephones, cordless telephones, automobiles, trains, etc. It has attractive features such as simple construction, sufficiently broadband characteristics for voice communication, small dimensions at high frequencies. Alternatives to the monopole antenna for hand-held units is the inverted F and L antennas, the microstrip patch antenna, loop and spiral antennas, and others. The printed inverted F antenna (PIFA) is arguably the
most common antenna design used in modern handheld phones.
(c) Nikolova 2016
Data Communications,Data Networks,computer communications,multiplexing,spread spectrum,protocol architecture,data link protocols,signal encoding techniques,transmission media
CDMA allows multiple communication channels to share the same frequency band by using unique coded signals called orthogonal codes or Walsh codes. Each station transmitting data is assigned a unique orthogonal code. The codes are multiplied with the data bits and combined at the transmitter. At the receiver, the combined signal is multiplied by each possible code. If it matches the code assigned to that station, the data bit value can be recovered. Using orthogonal codes in this way allows separation of the multiple communication channels in the shared frequency band.
Modulation is the process of putting information onto a carrier wave for transmission. It is needed if the medium is bandpass in nature or only a bandpass channel is available. There are three main types of analog modulation: amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM). AM varies the amplitude of the carrier wave, FM varies the frequency, and PM varies the phase. The frequency spectrum of an AM signal contains sidebands above and below the carrier frequency. The bandwidth is twice the modulating signal bandwidth.
This document discusses various topics related to radio wave propagation including:
1. Modes of propagation such as ground wave, sky wave, and space wave propagation. Sky wave propagation involves signal reflection from ionized layers in the atmosphere.
2. Characteristics of the ionospheric layers including the D, E, F1, and F2 layers which vary in ionization levels and affect the maximum usable frequency.
3. Key concepts in sky wave propagation such as virtual height, skip distance, maximum usable frequency, and how daylight impacts absorption and refraction of signals.
The document discusses bipolar junction transistors (BJTs). It describes the basic construction of an NPN and PNP transistor including the emitter, base, and collector regions. It explains that the base-emitter junction must be forward biased and the base-collector junction must be reverse biased for the transistor to operate. The document also discusses BJT biasing circuits, operating regions including cutoff, saturation, and active modes, and uses of BJTs as switches and amplifiers.
A varactor diode is a diode that has a variable capacitance based on the reverse bias voltage applied. It consists of a P-N junction with conductive P and N regions acting as capacitor plates, separated by a depletion region that acts as the dielectric. The capacitance varies inversely with the square root of the applied reverse voltage, decreasing as voltage increases. Varactor diodes are commonly used in communication systems to allow tuning of circuits by changing the capacitance.
Here are the solutions to the exercises:
1) For a GI fiber with parabolic profile, Vmax = 2.405 for single mode operation.
Using the given: n1 = 1.5, Δ = 1%, λ = 1.3 μm
Vmax = (2π/λ) * a * (n1^2 - n2^2)^1/2
= 2.405
Solving for a, the maximum core diameter is 5.2 μm.
2) Given: n1 = 1.54, n2 = 1.5, a = 25 μm, λ = 1300 nm
NA = (n1^2 - n2^2)^1/
The document discusses the ALOHA protocol for medium access. It was developed at the University of Hawaii in 1971 to connect users across the Hawaiian islands via radio frequencies. There are two main versions: Pure ALOHA, where nodes transmit randomly, and Slotted ALOHA, where time is divided into slots for transmission. Slotted ALOHA improves on Pure ALOHA by reducing collisions to only those within a time slot. The maximum throughput for Pure ALOHA is 18.4% while Slotted ALOHA achieves 37%, but both protocols experience exponentially decreasing performance with only small increases in network load.
Generation of SSB and DSB_SC ModulationJoy Debnath
The document discusses two methods of single sideband (SSB) modulation and balanced modulator modulation. It explains that SSB modulation eliminates one sideband from an amplitude modulated wave. It then describes the balanced modulator method, which uses two balanced modulators and a 90 degree phase shift to cancel out one sideband. The document also provides a brief overview of double sideband suppressed carrier (DSB-SC) modulation and notes that it uses two methods: multiplier modulation and balanced modulator.
The document discusses various techniques for line coding used to transmit digital data over communication channels. It describes several line coding schemes including unipolar, polar, and bipolar coding, as well as specific schemes like non-return to zero, return to zero, and Manchester coding. These coding techniques are used to represent digital signals for transmission and help address issues like inter-symbol interference caused by the band-limited nature of communication channels.
HDLC is a bit-oriented protocol that defines rules for transmitting data between network nodes. It supports full-duplex communication and organizes data into frames sent from a source to a destination. HDLC defines three station types - primary stations control data flow, secondary stations operate under primary control, and combined stations act as both. HDLC uses different frame types and operates in modes like normal response for point-to-point links and asynchronous balanced for communication between combined stations.
1) A VPN creates a secure connection over public networks to protect users' privacy and allow them to access blocked content. It works by extending a private network across the internet.
2) There are two main types of VPNs - remote access VPNs that allow users to remotely access a private network, and site-to-site VPNs that connect networks in different locations.
3) VPNs use encryption protocols like IPsec and SSL/TLS to securely tunnel traffic over the internet and authenticate users. This provides confidentiality, integrity, and sender authentication for VPN connections.
The document discusses discrete Fourier series, discrete Fourier transform, and discrete time Fourier transform. It provides definitions and explanations of each topic. Discrete Fourier series represents periodic discrete-time signals using a summation of sines and cosines. The discrete Fourier transform analyzes a finite-duration discrete signal by treating it as an excerpt from an infinite periodic signal. The discrete time Fourier transform provides a frequency-domain representation of discrete-time signals and is useful for analyzing samples of continuous functions. Examples of applications are also given such as signal processing, image analysis, and wireless communications.
- Class A amplifiers have high voltage gain but low efficiency, as the output transistor constantly conducts current even without an input signal.
- Class B amplifiers improve efficiency by using two transistors in a push-pull configuration, but suffer from crossover distortion as both transistors are briefly off at the same time during signal transitions.
- Class AB amplifiers reduce crossover distortion by applying a small bias voltage, so the transistors conduct slightly more than half of each cycle and efficiency is improved over Class A while minimizing distortion.
description of the services to the networks .
how to apply quality of service
how to improve the networks
summary in personal point of view
please don't hesitate if you have further question
Webinar Slides: Probing in Power Electronics - What to use and whyteledynelecroy
Join Teledyne LeCroy for this webinar as we provide an overview of the different HV rated probe specifications and topologies, explain what measurement each probe topology is ideally suited for, and provide real-word examples and comparisons between a variety of different probes and amplifiers.
Webinar Slides: Probing in Power Electronics - What to use and whyHilary Lustig
Join Teledyne LeCroy for this webinar as we provide an overview of the different HV rated probe specifications and topologies, explain what measurement each probe topology is ideally suited for, and provide real-word examples and comparisons between a variety of different probes and amplifiers.
Transmission line, single and double matchingShankar Gangaju
This document discusses different types of transmission lines used for transmitting energy and signals over long distances. It describes common transmission line media like twisted pair, coaxial cable and optical fiber. It covers their applications in telephone networks, buildings and computer networks. It also discusses their transmission characteristics and limitations. The document compares properties of unshielded and shielded twisted pair. It provides details on utilizing different wavelengths in optical fiber for various applications.
This document discusses peak-to-average power ratio (PAPR) reduction techniques for orthogonal frequency-division multiplexing (OFDM) signals. It begins with an introduction to PAPR and its causes for OFDM signals. It then outlines various PAPR reduction techniques including clipping, coding, probabilistic/scrambling, predistortion, and DFT-spreading. Each technique has benefits but also cons such as distortion, reduced efficiency, or increased complexity. The document provides analysis of PAPR characteristics for different OFDM parameters and modulation schemes.
The dipole and the monopole are arguably the two most widely used antennas across the UHF, VHF and lower-microwave bands. Arrays of dipoles are commonly used as base-station antennas in land-mobile systems. The monopole and its variations are common in portable equipment, such as cellular telephones, cordless telephones, automobiles, trains, etc. It has attractive features such as simple construction, sufficiently broadband characteristics for voice communication, small dimensions at high frequencies. Alternatives to the monopole antenna for hand-held units is the inverted F and L antennas, the microstrip patch antenna, loop and spiral antennas, and others. The printed inverted F antenna (PIFA) is arguably the
most common antenna design used in modern handheld phones.
(c) Nikolova 2016
Data Communications,Data Networks,computer communications,multiplexing,spread spectrum,protocol architecture,data link protocols,signal encoding techniques,transmission media
CDMA allows multiple communication channels to share the same frequency band by using unique coded signals called orthogonal codes or Walsh codes. Each station transmitting data is assigned a unique orthogonal code. The codes are multiplied with the data bits and combined at the transmitter. At the receiver, the combined signal is multiplied by each possible code. If it matches the code assigned to that station, the data bit value can be recovered. Using orthogonal codes in this way allows separation of the multiple communication channels in the shared frequency band.
Modulation is the process of putting information onto a carrier wave for transmission. It is needed if the medium is bandpass in nature or only a bandpass channel is available. There are three main types of analog modulation: amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM). AM varies the amplitude of the carrier wave, FM varies the frequency, and PM varies the phase. The frequency spectrum of an AM signal contains sidebands above and below the carrier frequency. The bandwidth is twice the modulating signal bandwidth.
This document discusses various topics related to radio wave propagation including:
1. Modes of propagation such as ground wave, sky wave, and space wave propagation. Sky wave propagation involves signal reflection from ionized layers in the atmosphere.
2. Characteristics of the ionospheric layers including the D, E, F1, and F2 layers which vary in ionization levels and affect the maximum usable frequency.
3. Key concepts in sky wave propagation such as virtual height, skip distance, maximum usable frequency, and how daylight impacts absorption and refraction of signals.
The document discusses bipolar junction transistors (BJTs). It describes the basic construction of an NPN and PNP transistor including the emitter, base, and collector regions. It explains that the base-emitter junction must be forward biased and the base-collector junction must be reverse biased for the transistor to operate. The document also discusses BJT biasing circuits, operating regions including cutoff, saturation, and active modes, and uses of BJTs as switches and amplifiers.
A varactor diode is a diode that has a variable capacitance based on the reverse bias voltage applied. It consists of a P-N junction with conductive P and N regions acting as capacitor plates, separated by a depletion region that acts as the dielectric. The capacitance varies inversely with the square root of the applied reverse voltage, decreasing as voltage increases. Varactor diodes are commonly used in communication systems to allow tuning of circuits by changing the capacitance.
Here are the solutions to the exercises:
1) For a GI fiber with parabolic profile, Vmax = 2.405 for single mode operation.
Using the given: n1 = 1.5, Δ = 1%, λ = 1.3 μm
Vmax = (2π/λ) * a * (n1^2 - n2^2)^1/2
= 2.405
Solving for a, the maximum core diameter is 5.2 μm.
2) Given: n1 = 1.54, n2 = 1.5, a = 25 μm, λ = 1300 nm
NA = (n1^2 - n2^2)^1/
The document discusses the ALOHA protocol for medium access. It was developed at the University of Hawaii in 1971 to connect users across the Hawaiian islands via radio frequencies. There are two main versions: Pure ALOHA, where nodes transmit randomly, and Slotted ALOHA, where time is divided into slots for transmission. Slotted ALOHA improves on Pure ALOHA by reducing collisions to only those within a time slot. The maximum throughput for Pure ALOHA is 18.4% while Slotted ALOHA achieves 37%, but both protocols experience exponentially decreasing performance with only small increases in network load.
Generation of SSB and DSB_SC ModulationJoy Debnath
The document discusses two methods of single sideband (SSB) modulation and balanced modulator modulation. It explains that SSB modulation eliminates one sideband from an amplitude modulated wave. It then describes the balanced modulator method, which uses two balanced modulators and a 90 degree phase shift to cancel out one sideband. The document also provides a brief overview of double sideband suppressed carrier (DSB-SC) modulation and notes that it uses two methods: multiplier modulation and balanced modulator.
The document discusses various techniques for line coding used to transmit digital data over communication channels. It describes several line coding schemes including unipolar, polar, and bipolar coding, as well as specific schemes like non-return to zero, return to zero, and Manchester coding. These coding techniques are used to represent digital signals for transmission and help address issues like inter-symbol interference caused by the band-limited nature of communication channels.
HDLC is a bit-oriented protocol that defines rules for transmitting data between network nodes. It supports full-duplex communication and organizes data into frames sent from a source to a destination. HDLC defines three station types - primary stations control data flow, secondary stations operate under primary control, and combined stations act as both. HDLC uses different frame types and operates in modes like normal response for point-to-point links and asynchronous balanced for communication between combined stations.
1) A VPN creates a secure connection over public networks to protect users' privacy and allow them to access blocked content. It works by extending a private network across the internet.
2) There are two main types of VPNs - remote access VPNs that allow users to remotely access a private network, and site-to-site VPNs that connect networks in different locations.
3) VPNs use encryption protocols like IPsec and SSL/TLS to securely tunnel traffic over the internet and authenticate users. This provides confidentiality, integrity, and sender authentication for VPN connections.
The document discusses discrete Fourier series, discrete Fourier transform, and discrete time Fourier transform. It provides definitions and explanations of each topic. Discrete Fourier series represents periodic discrete-time signals using a summation of sines and cosines. The discrete Fourier transform analyzes a finite-duration discrete signal by treating it as an excerpt from an infinite periodic signal. The discrete time Fourier transform provides a frequency-domain representation of discrete-time signals and is useful for analyzing samples of continuous functions. Examples of applications are also given such as signal processing, image analysis, and wireless communications.
- Class A amplifiers have high voltage gain but low efficiency, as the output transistor constantly conducts current even without an input signal.
- Class B amplifiers improve efficiency by using two transistors in a push-pull configuration, but suffer from crossover distortion as both transistors are briefly off at the same time during signal transitions.
- Class AB amplifiers reduce crossover distortion by applying a small bias voltage, so the transistors conduct slightly more than half of each cycle and efficiency is improved over Class A while minimizing distortion.
description of the services to the networks .
how to apply quality of service
how to improve the networks
summary in personal point of view
please don't hesitate if you have further question
Webinar Slides: Probing in Power Electronics - What to use and whyteledynelecroy
Join Teledyne LeCroy for this webinar as we provide an overview of the different HV rated probe specifications and topologies, explain what measurement each probe topology is ideally suited for, and provide real-word examples and comparisons between a variety of different probes and amplifiers.
Webinar Slides: Probing in Power Electronics - What to use and whyHilary Lustig
Join Teledyne LeCroy for this webinar as we provide an overview of the different HV rated probe specifications and topologies, explain what measurement each probe topology is ideally suited for, and provide real-word examples and comparisons between a variety of different probes and amplifiers.
Webinar: High Voltage Fiber Optic (HVFO) Probe for Small Signal Floating Meas...teledynelecroy
Join Teledyne LeCroy for this webinar as we provide an overview of the differences between a conventional high-attenuation HV differential probe, a HV isolated oscilloscope input, and the HVFO, along with some real-world measurement examples.
This document describes an experiment conducted on a small signal amplifier for a public address system. The objectives are to identify the role of an amplifier circuit in a PA system and to design, test, and analyze an amplifier circuit. The experiment involves designing a voltage divider biasing circuit, simulating the circuit in Multisim, and building the circuit on a breadboard. Key measurements taken include the quiescent current, voltage, and gain with and without a bypass capacitor. The results show that adding a bypass capacitor increases the gain while removing it reduces the gain due to increased degeneration.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
Webinar Slides: Probing Techniques and Tradeoffs – What to Use and Whyteledynelecroy
Engineers must commonly probe low and high frequency signals with high signal fidelity. Typical passive probes with high input impedance and capacitance provide good response at lower frequencies, but inappropriately load the circuit and distort signals at higher frequencies.
Join Teledyne LeCroy for this webinar as we discuss:
- Selecting the right probing techniques to maximize the accuracy of your measurements
- Probe specifications and their implications on the measured signal
- Variety of probes and accessories available for measurement
- Virtual probing software tools that allow the user to probe the signal when direct access is physically impossible
The document describes the design of a low power preamplifier integrated circuit for cochlear implants using a split folded cascode technique. This technique splits the input transistors into two branches with equal aspect ratios, increasing the overall transconductance by 1.414 times compared to a normal folded cascode. Simulations of the proposed preamplifier design in Cadence Virtuoso using a 180nm process show a mid-band gain of 43.7 dB, bandwidth of 18-20 kHz, and input-referred noise of 473.47 nV/√Hz at 4 kHz, while consuming 4.47 μW from a 1.8V supply. The split folded cascode technique enhances performance over normal cascode
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document provides a tutorial on designing microwave amplifiers using CAD software. It discusses:
1) The key steps in microwave amplifier design including selecting an active device, biasing it, characterizing the device, analyzing stability, and implementing matching networks.
2) Methods for stability analysis including the Rollett K-factor test, source-load circle graphical analysis on the Smith Chart, and evaluating the reflection coefficients Γin and Γout.
3) How CAD tools like AWR's Microwave Office can be used to design microwave amplifiers by simulating the circuit and evaluating performance based on the device specifications and design parameters.
UHF/VHFEnergy Harvesting Radio System Physical and MAC Layer Considerationxiaohuzhang
This is my defence slides. There are three parts been talked :
(1) Background and challenges on wireless sensor networks and nodes;
(2) Solutions for the challenges of wireless sensor nodes;
(3) Summary and future research directions.
This document is a project report submitted by Renu Gupta to fulfill requirements for a Master's degree in Electronics and Communication Engineering. The project involves realizing various signal processing and generating circuits using an Operational Trans-Resistance Amplifier (OTRA). The OTRA is implemented using commercially available CFOA ICs. Circuits designed include filters, oscillators, and an active inductor-based LC oscillator. Theoretical results are verified through PSPICE simulations and experiments using practical circuits assembled with CFOA ICs. The report documents the work conducted under the guidance of Dr. Neeta Pandey.
Low Power Design Techniques for ASIC / SOC DesignRajesh_navandar
1. Low power techniques aim to reduce both dynamic and static/leakage power in integrated circuits. Dynamic power is reduced through techniques like lowering supply voltage and clock frequency, while leakage power is reduced by increasing transistor threshold voltage.
2. Power gating is a widely used technique that temporarily turns off unused circuit blocks to drastically reduce leakage power. It requires additional power switches and isolation cells to safely turn blocks on and off.
3. Multi-threshold CMOS uses both low and high threshold voltage transistors optimized for performance and leakage respectively. Further scaling presents new challenges as leakage power becomes dominant.
A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V supply in ...aiclab
Pushed by the ever-increasing demand of high-speed connectivity, next generation 400Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits FFE, and allows tuning the output impedance to ensure good source termination. Implemented in 28nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >>2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s, while drawing 120mA only from 1V supply. The power efficiency is ~2 times better than previously reported PAM-4 transmitters.
Clipper circuits were studied including series, parallel, and dual clipper configurations. Various clipper circuits were simulated using Multisim software and tested using hardware. Key aspects:
1) Series, parallel, and dual clipper circuits were designed to clip either the positive or negative portions of input signals.
2) Biased and unbiased clipper circuits were analyzed both in simulation and using hardware. External biasing was applied to parallel clipper circuits.
3) Input signals of 5V were clipped in various ways depending on the circuit configuration and applied biases. Output waveforms were observed on an oscilloscope.
4) Clipper circuits have applications in limiting signal amplitudes for applications like FM radio
Power supplies convert alternating current (AC) to direct current (DC) using components like transformers, rectifiers, and filters. Common rectifier types include half-wave, full-wave center-tapped, and full-wave bridge rectifiers. Filters use inductors and capacitors to smooth the pulsating DC output into a steady DC voltage. Safety is important when working with power supplies, as filter capacitors can hold a charge even after power is turned off. Switching power supplies are more efficient than linear supplies and are commonly used in electronics today.
Implementation of Simple Wireless NetworkNiko Simon
End of course project where students were given free rein to explore wireless concepts through analysis of theory and hardware builds. The transmitter sends a Morse code audio signal which is then outputted by the receiver. Test of Morse code output: https://youtu.be/-06qOH7lYCg
DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13UM RF CMOS TECHNOL...VLSICS Design
This two-stage power amplifier was designed in 0.13um RF CMOS technology for 2.4GHz WLAN applications. It consists of a driver stage using a cascode topology and a power stage using a basic topology. At 1dB compression, it delivers 20.028dBm of output power with 44.669% power added efficiency. Maximum output power is 22.002dBm with 70.196% efficiency. Input and output return losses are -11.132dB and -12.467dB respectively, with a gain of 43.745dB at 1dB compression.
Variable Frequency on Wireless Power Transfer for Pacemaker using Embedded Te...IRJET Journal
This document describes a proposed wireless power transfer system for powering implantable medical devices like pacemakers. It discusses the challenges with using batteries in implants and proposes using inductive coupling between an external coil and implanted coil for contactless power transfer. The system would use a microcontroller to control power transmission frequency and rectifiers to convert the received AC power to DC for use in the implant. Design considerations like coil sizes, capacitors for impedance matching, and efficiency are analyzed. The document outlines the various circuit components that would be needed for the transmitter, receiver, and power regulation components for a wireless power transfer system for medical implants.
This document summarizes some key challenges for digital circuits related to process, voltage, and temperature variations. It discusses techniques to prevent latchup and electrostatic discharge issues in integrated circuits. It also describes simultaneous switching noise that can occur when large numbers of circuits switch simultaneously. The document proposes using adaptive body biasing techniques to compensate for PVT variations and control output slope under different conditions. Simulation results show this approach can adjust rising and falling times of an output buffer for different substrate bias voltage conditions.
1) The document describes the design and simulation of a linear amplifier that operates in the C band frequency range of 5-6 GHz.
2) A Class A amplifier design approach was used to ensure linearity at higher frequencies. A GaAs FET transistor was selected and biased in its linear region.
3) Input and output matching networks were designed using S-parameter simulations. Multiple transistor stages were cascaded to increase the gain to 30 dB.
4) Simulation results showed a gain of 19.241 dB, S-parameters, stability above 1, and a noise figure of around 3 dB as expected for a low noise pre-amplifier.
Efficient signal acquisition in multi channel neural systemsAshwath Krishnan
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Webinar Slides: Digital Power Management and Power Integrity Analysis and Testing
1. WEBINAR:
Digital Power Management,
Power Integrity, and Power Rail Sequence
Analysis & Testing
March 2nd, 2017
Thank you for joining us. We will begin at 1:00pm EST.
NOTE: This presentation includes Q&A. We will be taking
questions during the presentation with answers at the end
using the questions section of your control panel.
March 2, 2017 1
2. Teledyne LeCroy Overview
March 2, 2017 2
LeCroy was founded in 1964 by Walter
LeCroy
Original products were high-speed digitizers
for particle physics research
Corporate headquarters is in Chestnut Ridge,
NY
Long history of innovation in digital
oscilloscopes
First digital storage oscilloscope
Highest bandwidth real-time oscilloscope
(100 GHz)
LeCroy became the world leader in protocol
analysis with the purchase of CATC and
Catalyst
Frontline Test Equipment and Quantum
Data were also recently acquired (2016)
In 2012, LeCroy was acquired by Teledyne
Technologies and renamed Teledyne
LeCroy
3. • Product Manager with Teledyne LeCroy
for over 15 years
• B.S., Electrical Engineering from
Rensselaer Polytechnic Institute
• Awarded three U.S. patents for in the
field of simultaneous physical layer and
protocol analysis
Ken Johnson
Director of Marketing, Product Architect
Teledyne LeCroy
ken.johnson@teledynelecroy.com
March 2, 2017 3
About the Presenter
4. Digital Power Management,
Power Integrity, and Power Rail Sequence
Analysis & Testing
Test single or multi-phase digital power management ICs (PMICs),
voltage regulator modules (VRMs), point-of-load (POLs) switching
regulators, low-dropout (LDO) regulators or other DC-DC converter
operations under transient load conditions, and test complete
embedded systems that contain these devices.
March 2, 2017 4
5. Agenda
Overview
Acquiring DC Voltage/Power Rails
Transient Rail Response Analysis
Single Rail
Multiple Rails
Multi-phase PMIC DC-DC Converter Current Sharing/Tracking Analysis
Voltage/Power Rail Sequence Testing
Power Integrity Measurement and Debug Examples
Summary
Questions
March 2, 2017 5
8. This Webinar’s Focus is on the Following
Digital Power Management
The control of various DC-DC converter voltages to
ensure appropriate and prompt delivery of current
(power) over one or more DC power/voltage rails to
various CPU, memory, or other devices in a
motherboard or embedded computing system.
Power Integrity
The analysis to determine whether expected voltage
and current requirements are met from regulated DC
output to the power consuming device.
Voltage/Power Rail Sequence Testing
The control of the ramp times and sequence of the
various DC power/voltage rails in a motherboard or
embedded computing system.
March 2, 2017 8
9. Digital Power Management Overview
An embedded computing
system requires one or
more different “rails” (e.g.,
3.3, 1.8, 1.5, 1.1Vdc) to
provide voltage and
current to the CPU and
other on-board devices.
Bulk power is supplied to
an embedded computing
system through a high
voltage (e.g., 12Vdc)
bus/supply.
To provide high efficiency,
each DC-DC converter power
supply is actually several
DC-DC converters in parallel.
In this example, there are four
parallel DC-DC converters
(called “phases” or “channels”)
that each supply 25% of the
total output current to the
1.1Vdc rail.
A Power Management IC
(PMIC) turns the phases
on and off as load power
requirements change, and
time interleaves the PWM
outputs into one output.
The PMIC and CPU are both located
on a motherboard of some type. The
motherboard may be part of a larger
stand-alone embedded system, or it
could be used in a server, laptop,
tablet, mobile phone, gaming system,
consumer device, etc.
4 “phase” or
“channel”
outputs from
one DC-DC
converter
1 DC power /
voltage rail
March 2, 2017 9
PMIC
The CPU issues
serial data
commands to the
PMIC so as to
ensure proper
current supply to
all devices
10. Digital Power Management and Power Integrity
Half-bridge output
The half-bridge output
current is commonly
called the “inductor
current” because it
flows through the output
inductor (filter).
It increases (ramps up)
when PWM signals are
“ON” and ramps down
when PWM signals are
“OFF”
Additional load
capacitance will filter
this further
March 2, 2017 10
11. Digital Power Management and Power Integrity
Ideal operation of multiple PMIC phases
Ideally, each PMIC phase under
steady-state load condition is
balanced
Same amplitude (voltage PWM)
Phase relationship to other
phases of (1/fs)/N
fs is the power semiconductor
device switching frequency
N is the number of phases
Example - these are the phase currents under steady-
state operating conditions after filtering by the inductor
March 2, 2017 11
12. Digital Power Management and Power Integrity
Non-ideal operation of multiple phases
If there are amplitude errors
between the different phases,
output ripple will result
If there are amplitude and phase
errors between the different
phases, more complicated
distortion patterns will be
introduced
March 2, 2017 12
13. First Polling Question (choose one or more)
What products are you designing and testing?
Multi-phase Digital Power Management ICs (PMICs)
VRM, POL or LDO regulators
Unregulated DC supplies
Embedded Systems using one or more of the above
None of the above
March 2, 2017 13
15. Acquiring DC Power/Voltage Rails
There are three methods (but only one very good method)
1. 50Ω Coaxial Cable Terminated at
Oscilloscope Input with DC 1MΩ
Coupling
Reasonable noise performance, but…
Requires high offset capability in the
oscilloscope…. or requires use of a DC
block (not ideal)
Reflections due to impedance
mismatch
Bandwidth limitations
2. Conventional 10x Passive Probe
Poor noise performance
Bandwidth limitations
Maximum gain setting limitations
3. Use of Specialized Active Voltage
Rail Probe
Ideal solution – lowest noise, highest
bandwidth, lowest circuit loading
March 2, 2017 15
16. Acquiring DC Power/Voltage Rails
Using a coaxial cable input terminated in 1 MΩ at the oscilloscope input
Requires large native offset capability
in the oscilloscope
HDO offset capability is very large
(more than any other oscilloscope)
+/-1.6V (1mV to 4.95mV/div)
+/-4.0V (5mV to 9.9mV/div)
+/-8.0V (10mV to 19.8mV/div)
+/-10.0V (20mV to 1V/div)
Or requires a DC block
DC blocks don’t pass all AC
frequencies
1 MΩ oscilloscope termination has
limitations
Frequency response <1 GHz
Reflections due to impedance
mismatch
Signal input via coaxial
cable to Teledyne
LeCroy HDO
Same signal as above
with 1.8 V offset and gain
of 5 mV/div
March 2, 2017 16
1.8 V
0 V
1 V/div
5 mV/div
0 V offset
1.8 V offset
1.8 V
0 V
17. Acquiring DC Power/Voltage Rails
What’s wrong with using a conventional 10x passive probe?
Passive Probes have 10x attenuation
Therefore, the oscilloscope gain setting is
1/10th that of the desired gain setting
This has the following impacts on the
measurement:
Increased noise
what is attenuated must be amplified
Reduced offset capabilities
Offset capability is determined by underlying
oscilloscope gain setting
Higher maximum gain setting
i.e., an oscilloscope with a 1 mV/div maximum
gain setting used with a 10x probe will have a
10 mV/div probe+oscilloscope maximum gain
setting
Additionally, the Passive Probe also has
bandwidth limitations
1 MΩ oscilloscope terminations limit
frequency response to <1 GHz
Passive Probe frequency response is typically
~500 MHz (maximum)
March 2, 2017 17
1.8 V
0 V
1 V/div
10 mV/div
0 V offset
1.8 V offset
1.8 V
0 V
Signal input via
Passive Probe to
Teledyne LeCroy HDO
Same signal as above
with 1.8 V offset and gain
of 10 mV/div
18. Acquiring DC Power/Voltage Rails
What’s wrong with using a conventional 10x passive probe? (continued)
This is the same example as the
previous slide, but with a vertical
zoom of Channel 1
Z1 = Zoom(C1)
Gain of vertical zoom is set to be
equal to 5 mV/div
Creates direct comparison to
previous coaxial cable input
example and next (rail probe)
example.
March 2, 2017 18
1.8 V
0 V
1 V/div
5 mV/div
0 V offset
1.8 V offset
1.8 V
0 V
Signal input via
Passive Probe to
Teledyne LeCroy HDO
Same signal as above with
1.8 V offset and vertically
zoomed to 5 mV/div
19. Acquiring DC Power/Voltage Rails
Using a specialized Rail Probe
Provides four important capabilities for rail
voltage acquisitions:
50 kΩ Input Impedance
Very low circuit loading on the DC rail
1.2x Attenuation
Keeps scope+probe noise very low
~165 μVrms at 1 GHz and 1 mV/div
(HDO)
+/-30V Offset built-in
Center a DC signal and use a high-
sensitivity gain setting (e.g., 1-20 mV/div)
4 GHz of bandwidth
+/-800 mV dynamic/differential range
Offset must be applied or a >800mV signal
will not appear on the oscilloscope grid
Can also be re-purposed for full dynamic
range voltage/power rail acquisitions
Use an SMA to BNC adapter and attach
directly to BNC input with 1 MΩ coupling
March 2, 2017 19
1.8 V
0 V
200 mV/div
5 mV/div
0 V offset
1.8 V offset
1.8 V
0 V
Signal input via
RP4030 Active Voltage
Rail Probe to Teledyne
LeCroy HDO
Same signal as above
with 1.8 V offset and gain
of 5 mV/div
20. Acquiring DC Power/Voltage Rails
Comparison summary from previous four slides
March 2, 2017 20
Coaxial Cable Input
Terminated at 1 MΩ
February 1, 2017 20
5 mV/div 1.8 V offset
1.8 V
0 V
5 mV/div 1.8 V offset
1.8 V
0 V
Passive Probe
5 mV/div 1.8 V offset
1.8 V
0 V
Active Voltage Rail Probe
Best
Solution
21. RP4030 Active Voltage/Power Rail Probe
A wide variety of tips and leads for DUT connection are supplied
ProBus-
compatible
amplifier MCX PCB Mounts (4 GHz)
(good for larger circuit boards – attach and leave
in place for quick and easy connection to cable)
MCX Solder-in Lead (4 GHz)
(can be soldered-in and left in circuit)
SMA to MCX
short cable
March 2, 2017 21
MCX to U.FL Lead (3 GHz)
(attaches to compact U.FL PCB
Mounts).
MCX to SMA Adapter
U.FL PCB Mounts
(compact size for dense, mobile or
handheld systems)
22. RP4030 Equivalent Circuit Diagram
The RP4030 probe is shaded in gray, and the cable and oscilloscope are not shaded
March 2, 2017 22
High Bandwidth
SMA Connector
MCX Termination
Provides Flexibility
for DUT Connection
High DC Input Impedance
(Low DUT Loading) with Low
High Frequency Input
Impedance
High precision, high
dynamic range offset DAC
(16-bit, 30V)
Auto Zero of Probe Can be
Done While Connected to DUT
23. RP4030 U.FL Solution for Compact PCBs
Hirose U.FL ultra-miniature PCB
mounts can be designed in to
make probing easy
3mm x 3mm
Functionally equivalent to IPX
and UMCC connectors
3 GHz
Low cost
March 2, 2017 23
Removal is simple with a widely
available special-purpose
extraction tool
24. RP4030 Solder-in Lead
Solder-in Lead Provides
Optimum Performance
4 GHz
Reasonable cost
Multiple Leads Can be Soldered-
in and Left in Place
March 2, 2017 24
25. RP4030 Optional Browser
SMA to SMA
Cable
(for connecting to the
RP4030 ProBus
compatible amplifier)
SMA to BNC
Adapter
(for connecting directly to a
scope BNC input if used as
a PP066 Transmission
Line Probe)
Browser Tip with
0Ω Resistor
(for low attenuation, good
noise performance)
450Ω and 950Ω
Resistors
(for use as 10x or 20x
PP066 equivalent)
March 2, 2017 25
26. Other Teledyne LeCroy Voltage and Current Probes
That are commonly used in Digital Power Management and Power Integrity Testing
Differential Amplifiers (DA1855A)
and Probes (AP033) with 10x
Gain
Ideal for shunt/series resistor
measurements
Up to 100 dB CMRR
High Sensitivity Current Probes
50 or 100 MHz
Low-cost 1 GHz Active FET
Probe
Great for general probing or
power sequence testing
March 2, 2017 26
27. 10x Gain Differential Voltage Probe for Series/Shunt Resistor
Top is a conventional diff probe, bottom is a CMRR optimized probe amplifier with 10x gain
March 2, 2017 27
28. Second Polling Question (choose one or more)
What types of probes do you use today to probe DC power/voltage
rails?
Coaxial cables (50Ω input coupled to oscilloscope)
Coaxial cables (1MΩ input coupled to oscilloscope)
Conventional 10x passive probes
Conventional single-ended active voltage probes
Active voltage rail probe (power rail probe)
March 2, 2017 28
30. Typical Digital Power Management and Power Integrity Tests
For One PMIC (One DC Voltage/Power Rail)
PMIC Transient DC Rail Response
Addition or release (subtraction) of load
Dynamic test
Long capture time is very useful
Correlate activity to other signals
Serial data commands
Clocks / Strobes
Enable lines
Measure DC Rail and Ensure that
Tolerances are Met
Mean voltage value
Ripple
Ringing
Peak+ and Peak-
Settling Time
Droop
DC Rail
March 2, 2017 30
31. Example of Commonly Measured Voltage/Power Rail Parameters
March 2, 2017 31
7 mV/div
993 mV offset
Droop
Ripple
(Periodic and Random Disturbances)
Settling
Ripple
Current
Transient
Peak -
Recovery
Time
32. PMIC Transient Rail Response Testing
Acquiring and Viewing the Transient Response of a Single DC Rail
Load increased
from ~0 to 20A
DC Rail voltage
transient response
is monitored
7 mV/div gain setting
with 1Vdc offset
March 2, 2017 32
20A
No-load (near 0A)
Mean DC = 999.67mV
Mean DC = 1003mV
Load current
1.0V multi-phase rail
Acquired using the
RP4030 Active Voltage
Rail Probe
Acquired using the
CP030A High-sensitivity
Current Probe
33. PMIC Transient Rail Response Testing, cont’d
Quantifying the Transient Response of a Single DC Rail with Measurement Parameters
Measurement
Parameters with Gates
can be used to measure
VdcRAIL before and after
load.
999.67 mV before
1003.00 mV after
Zooms and
measurement
parameters can be used
to understand high-
frequency behaviors
Z1 = VMIN at step
(967.70 mV)
Z5 = VMAX before
step (1012.21 mV)
Z7 = VMAX after step
(1016.38 mV)
Measure Parameter can
be used to measure
step load change
20.436 A
March 2, 2017 33
DC Rail Current
DC Rail Voltage
Mean DC = 999.67mV
Mean DC = 1003mV
12-bit
Resolution
34. PMIC Transient Rail Response Testing, cont’d
Per-cycle Waveforms and Numerics to understand rail behaviors (DIG-PWR-MGMT option)
March 2, 2017 34
Load current
Mean Value
Numerics Table
of 1V Rail
Acquired
Waveforms
Per-cycle
Calculated
WaveformsThese waveforms have one calculated
value for one per-cycle calculation period.
1.0V multi-phase rail
36. PMIC Transient Rail Response Testing, cont’d
Multiple PMICs and Multiple DC Rails
Same Tests as Single Rail Case
Objective is to Understand
Impacts of Load Changes on All
Rails at One Time
Clocks / Strobes
Enables
Serial Data, etc.
DC Rail 1
DC Rail 2
DC Rail 3
DC Rail 4
+
March 2, 2017 36
37. PMIC Transient Rail Response Testing, cont’d
Acquiring and Viewing the Transient Response of a Load Release on Multiple Rails
Monitored input
signals included
Simple DC Rails
700mV
900mV
1.2V
1.5V
Multi-phase DC
Rail (1.0V)
12V supply Rail
Load Current
(20A to 0A)
PWM Clock
March 2, 2017 37
PWM Clock Frequency
900mV rail
700mV rail
1.5V rail
1.2V rail
1.0V multi-phase rail
12V input supply
Load current
38. PMIC Transient Rail Response Testing, cont’d
Digital Power Management (DIG-PWR-MGMT) Software Provides More Information
March 2, 2017 38
PWM Clock Frequency
(used to determine period over which
calculations can be made)
900mV rail
700mV rail
1.5V rail
1.2V rail
1.0V multi-phase rail
12V input supply
Load current
Mean Value
Numerics Table
Acquired
Waveforms
Calculated
Waveforms
Q-Scape
Tabbed
Display
Mean DC rail values calculated once per
PWM clock cycle and plotted over time,
time-correlated to original acquisitions.
Mean DC values of 1.0V rail
more clearly shows settling time
and rail droop.
Load release on 12V supply can
be clearly observed as an 80mV
voltage increase with an improved
voltage tolerance (sdev).
39. PMIC Transient Rail Response Testing, cont’d
Zoom+Gate provides capability to understand details of system response
March 2, 2017 39
PWM Clock Frequency
(used to determine period over which
calculations can be made)
Load current
Mean Value
Numerics Table
50x Zooms
of Acquired
Waveforms
50x Zooms
of Calc’d
Waveforms
These alternating color-coded highlights
indicate the identified periods we are
making the per-cycle calculations during.
These waveforms have one calculated
value for one per-cycle calculation period.
41. PMIC Transient Rail Response Testing, cont’d
For Multiple Phases in One PMIC
PMIC Load/Current Sharing/Tracking
Measure voltage/current on each
individual phase output
Difficult to do – PMIC normally does not
make output accessible for measuring
current
Phase 1
Phase 4
Phase 3
Phase 2
March 2, 2017 41
42. Combined Research Project (Oracle + Teledyne LeCroy)
“A Generic Test Tool for Power
Distribution Networks”
Dr. Istvan Novak
Senior Principal Engineer, Oracle
Peter Pupalaikis
VP Technology Development,
Teledyne LeCroy
Presented February 2, 2017 at
DesignCon 2017 in Santa Clara,
California (USA)
http://cdn.teledynelecroy.com/files/
whitepapers/designcon-2017-a-
generic-test-tool-for-power.pdf
March 2, 2017 42
45. Potential variables:
DC load current
DC input voltage
DC output voltage
Temperature
AC excitation current
Impedance magnitude [Ohm]
Output Impedance vs. DC Load Current (Light Load)
March 2, 2017 45
49. What is Sequence Testing?
For the computing system to
“boot-up” correctly, the DC rails
must turn ON in a specific order
with specific “wait times”
between each turn ON.
For example,
First 3.3Vdc goes high
Then, 200-500ms later, 1.8Vdc
goes high
Then 200-500ms later, 1.5Vdc
goes high
Lastly, 500ms-800ms later,
1.1Vdc goes high
March 2, 2017 49
50. What are Sequencing Tests?
Acquire as many DC rail signals as
possible
More is better – great 8ch application
Acquire other signals, e.g.:
Clocks
PMIC enable
Strobes
Serial data command signals to PMIC
Measure timing between signals
Usually with cursors
Serial TDME options could be useful to
some customers
Long capture times with high SR are
common
250 Mpts of memory is very useful
Capture a lot of time at high sample
rate in many different start-up
scenarios, and zoom for details
The image above is a start-up sequencing requirement
(timing details are omitted) for a TI embedded ARM
microprocessor (http://www.ti.com.cn/product/cn/AM3358-
EP/datasheet/6_ZHCSE24A
Note the many different rail voltages (5 different) and
multiple 1.8Vdc rails – this is very common
Important reason why 8ch is very, very useful
March 2, 2017 50
51. Voltage/Power Rail Sequence Testing on Power Down
50 Mpt capture at 250 MS/s (200 ms) – using timing parameters to measure delta times
March 2, 2017 51
900mV rail
700mV rail
1.5V rail
1.2V rail
1.0V multi-phase rail
Unregulated 1.0V rail
Load current
Measurements of
Delay Time from Ch3
Going Low to Other
Rails Going Low
Scope trigger set to first rail known to go low.
1.0V multi-phase rail
Unregulated 900mV rail
52. Voltage/Power Rail Sequence Testing – Using Serial Data Toolsets
Trigger on a Serial Data Message, Decode It, and Make Automated Timing Measurements
March 2, 2017 52
900mV rail
700mV rail
1.5V rail
1.2V rail
Unregulated 1.0V rail
Load current
Serial Data message
initiates power-up
1.0V multi-phase rail
Unregulated 900mV rail
Time from serial data message to
power up calculated using
automated parameter and decoded
serial data.
Decoded serial data message that
initiated sequencing activities
53. Serial Data Toolsets – Measurements and Graphing
Timing Measurements
Message to Analog
Analog to Message
Message to Message
Message to Value
“Serial DAC”
Automatic
Run corner cases,
gather statistics
Display histograms
Correlate cause-effect
timing relationships to
other events
March 2, 2017 53
54. Message to Value
parameter
View serial data
change over time
Examples
PMbus voltage
I2C or SPI
temperature
CAN steering
wheel angle
CAN wheel
speed (ABS)
I2S audio
“Serial Data DAC” Graphing of Digitally Decoded Data
March 2, 2017 54
Serial Data messages
(100s or 1000s)
Track of Message to Value
parameter
Message to Value
parameter
55. SPMI (System Power Management Interface) Decoder
SPMI
MIPI standard
More than 20+
other complete
solutions
I2C (PMbus)
UART-RS232
SPI
USB2
HSIC
etc.
March 2, 2017 55
57. Power Integrity
Measurement and Debug Example 1
Jitter on a 10 MHz clock circuit is traced back to a
2.9 MHz Point-of-load (POL) DC-DC converter
March 2, 2017 57
58. Overview of DUT
Power Delivery System for a Wireless Router
Switched-mode
AC-DC power
supply
Point-of-Load
(POL) DC-DC
converter
Power delivery
network
March 2, 2017 58
59. 2.9 MHz POL DC-DC Converter Spectral Measurements
The oscilloscope Spectrum Analyzer capability is used to frequency peaks of the POL
March 2, 2017 59
Short Acquisition @ 20 GS/s
Long Acquisition
250 MS/s
Spectrum
Analyzer
Table
Peak Markers
Correspond to Table
60. POL Ripple Contributes to Clock Jitter
JitterKit can be used to quantify jitter on 10 MHz clock and trace it back to the POL
March 2, 2017 60
10 MHz clock acquisition (500 μs long)
TIE Jitter vs. time for the 10 MHz clock
TIE Jitter Overlay of
10 MHz clock
acquisition
TIE Jitter Spectrum of 10
MHz Clock
Histogram of TIE
measurements
Spectrum
Analysis
Table from
2.9 MHz POL
61. Power Integrity
Measurement and Debug Example 2
Understanding the impact of the power delivery
network (PDN) impedance on clock jitter coupling
March 2, 2017 61
62. Background - The Importance of Impedance
+
-
+ + + +
+
LoadVRM
Bulk Caps Decoupling
Caps
Capacitance
of Planes
Package
Package Lead
Inductance
Control Loop
Inductance
+
-
LoadVCC
Impedance
of PDN
VChip
ZPDN
IMax
Vcc ≠ VChip
March 2, 2017 62
63. An LDO DC-DC Converter Supplies Power to 10 and 125 MHz Clocks
March 2, 2017 63
64. Impedance – Measurement Example
+
-
LoadVCC
Impedance
of PDN
VChip
ZPDN
IMax
March 2, 2017 64
Power Rail Voltage
Measured at VCC
Power Rail Voltage
Measured at VCHIP
65. 10 MHz Clock Causing Ripple on Input Voltage Rail (VCC)
March 2, 2017 65
Long acquisition of VCC
Spectrum Analysis of VCC
Spectrum Analysis
Table of VCC
66. 10 MHz Clock Induced Ripple on VCC Impacts 125 MHz Clock
Ripple adds 1ps of jitter on the output of the125 MHz clock
March 2, 2017 66
TIE Jitter Spectrum of 125
MHz Clock
Histogram of TIE
measurements
This is a TIE jitter analysis of the 125 MHz clock
(the original acquisition is not shown)
67. Measuring Impedance of the PDN
The plot indicates the impact of the ESR and ESL on the circuit
Omicron Bode 100
40 MHz Network
Analyzer
March 2, 2017 67
Image source http://www.powerelectronictips.com/ceramic-or-
electrolytic-output-capacitors-in-dcdc-converters-why-not-both/
Power/Voltage Rail behaviors during load
changes correlate to PDN impedance
Equivalent series resistance (ESR) and
inductance (ESL) for half-bridge output
capacitor (COut)
Voltage transients at load changes are
primarily caused by ESL or impedance of
the output cap at very high frequencies.
Slew rates impacted by the reactive power
of the capacitor (QC)
68. A Decoupling Capacitor Can Be Used to Lower Impedance
TIE jitter is reduced by more than 1psrms in this example
March 2, 2017 68
S301-2 ON w/o
decoupling C
S301-2 ON w/
decoupling C
69. Power Integrity
Measurement and Debug Example 3
High clock jitter and malfunction can be seen to be
caused by POL DC-DC converter voltage droop.
March 2, 2017 69
70. POL DC-DC Converter Transient Load Response
This provides information about the impedance of the PDN
March 2, 2017 70
Load Current
(acquired with a differential voltage probe
and not rescaled to amps)
POL Output Voltage
dI/dt Calculated Waveform
single-phase operation single-phasemulti-phase operation
71. Transient Load Response Jitter Analysis
The POL output voltage droop to the clock causes large clock jitter
March 2, 2017 71
TIE Jitter Overlay of 10 MHz clock acquisition
This persistence overlay of the clock cycles shows very little
jitter with a small number of clock edges having significant jitter
TIE Jitter vs. time for the 10 MHz clock
Jitter can be seen to vary significantly during voltage droop
200ps TIE Jitter
per vertical
division
POL Output Voltage to 10 MHz clock vs. time
100mV droop occurs during step load
Jitter is quantified with
Time Interval Error
measurement. Peak to
peak jitter is 1ns
which is 1/8 of a
period
72. Transient Load Response – Power Switched on to a Second Clock
Load of second clock causes POL voltage droop and impacts 10 MHz clock functioning
March 2, 2017 72
POL Output Voltage to 10 MHz clock vs. time
Zoom of
above trace
10 MHz Clock Voltage vs. time
Zoom of above trace
73. Third Polling Question (choose one or more)
What types of testing do you do?
Analysis of a single or multiple voltage/power rail(s)
Multi-phase current tracking/sharing
Power rail sequence testing and timing
Embedded system debug for some/all of the above
None of the above
March 2, 2017 73
75. Teledyne LeCroy Equipment
for Digital Power Management, Power Integrity, and Power Sequencing Test and Analysis
March 2, 2017 75
4 or 8 channel, 12 bit, 1 GHz
Oscilloscopes
Comprehensive Probe Offering
DIG-PWR-MGMT
Digital Power Management
Analysis Software Option
Serial Trigger, Decode,
Measure/Graph and Eye Diagram
(TDME) Options
4 channel, 10 bit, 4 GHz
Oscilloscopes
JITKIT
Jitter Kit Toolbox Analysis
Software Option
SPECTRUM
Spectrum Analyzer software
(standard on most HDOs)
76. Questions?
You can also reach the presenter at
ken.johnson@teledynelecroy.com
March 2, 2017 76