This document discusses PCI Express based solid state drives (SSDs) for data centers. It covers the growth opportunity for PCIe SSDs, topology options using various form factors like SFF-8639 and M.2, and validation tools. It also discusses hot plug support on Intel Xeon processor based servers and upcoming industry workshops to advance the PCIe SSD ecosystem.
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
Moving to PCI Express based SSD with NVM ExpressOdinot Stanislas
Une très bonne présentation qui introduit la technologie NVM Express qui sera à coup sure l'interface du futur (proche) des "disques" SSD. Adieu SAS et SATA, bienvenu au PCI Express dans les serveurs (et postes clients)
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
This deck includes presentations made during the CXL Forum at Flash Memory Summit 22 delivered by AMD, Intel, NVIDIA, The CXL Consortium, The Open Compute Project, Marvell, MemVerge, Micron, SK hynix, Samsung, and VMware
During the CXL Forum at OCP Global Summit, Mahesh Wagh, CXL Consortium TTF Co-chair and Senior Fellow at AMD, presented and update of the CXL Consortium mission and road map.
Moving to PCI Express based SSD with NVM ExpressOdinot Stanislas
Une très bonne présentation qui introduit la technologie NVM Express qui sera à coup sure l'interface du futur (proche) des "disques" SSD. Adieu SAS et SATA, bienvenu au PCI Express dans les serveurs (et postes clients)
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
All Presentations during CXL Forum at Flash Memory Summit 22Memory Fabric Forum
This deck includes presentations made during the CXL Forum at Flash Memory Summit 22 delivered by AMD, Intel, NVIDIA, The CXL Consortium, The Open Compute Project, Marvell, MemVerge, Micron, SK hynix, Samsung, and VMware
An Introduction to eBPF (and cBPF). Topics covered include history, implementation, program types & maps. Also gives a brief introduction to XDP and DPDK
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
eBPF is an exciting new technology that is poised to transform Linux performance engineering. eBPF enables users to dynamically and programatically trace any kernel or user space code path, safely and efficiently. However, understanding eBPF is not so simple. The goal of this talk is to give audiences a fundamental understanding of eBPF, how it interconnects existing Linux tracing technologies, and provides a powerful aplatform to solve any Linux performance problem.
During the CXL Forum at OCP Global Summit, MemVerge CEO Charles Fan presented accomplishments of the CXL industry since 2019, the development of concept cars occurring today, and his predictions for the future of CXL
The Linux kernel is undergoing the most fundamental architecture evolution in history and is becoming a microkernel. Why is the Linux kernel evolving into a microkernel? The potentially biggest fundamental change ever happening to the Linux kernel. This talk covers how companies like Facebook and Google use BPF to patch 0-day exploits, how BPF will change the way features are added to the kernel forever, and how BPF is introducing a new type of application deployment method for the Linux kernel.
Kubernetes Architecture - beyond a black box - Part 2Hao H. Zhang
This continues the Kubernetes architecture deep dive series. (Part 1 see https://www.slideshare.net/harryzhang735/kubernetes-beyond-a-black-box-part-1)
In Part 2 I'm going to cover the following:
- Kubernetes's 3 most import design choices: Micro-service Choreography, Level-Triggered Control, Generalized Workload and Centralized Controller
- Default scheduler limitation and community's next step
- Interface to production environment
- Workload abstraction: strength and limitations
This concludes my work and knowledge sharing about Kubernetes.
"Session ID: BUD17-400
Session Name: Secure Data Path with OPTEE - BUD17-400
Speaker: Mark Gregotski
Track: LHG
★ Session Summary ★
LHG is using the ION-based secure memory allocator integrated with OPTEE as the basis for secure data path processing pipeline. LHG is following the W3C EME protocol and supporting Content Decryption Modules (CDMs) from Widevine and PlayReady.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-400/
Presentation: https://www.slideshare.net/linaroorg/bud17400-secure-data-path-with-optee
Video: https://youtu.be/6JdzsWZq4Ls
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
Keyword: LHG, secure-data, OPTEE
http://www.linaro.org
http://connect.linaro.org
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
Linux is usually at the edge of implementing new storage standards, and NVMe over Fabrics is no different in this regard. This presentation gives an overview of the Linux NVMe over Fabrics implementation on the host and target sides, highlighting how it influenced the design of the protocol by early prototyping feedback. It also tells how the lessons learned during developing the NVMe over Fabrics, and how they helped reshaping parts of the Linux kernel to support NVMe over Fabrics and other storage protocols better."
This presentation was delivered at LinuxCon Japan 2016 by Christoph Hellwig
It describes the MMC storage device driver functionality in Linux Kernel and it's role. It explains different type of storage devices available and how they are handled from MMC driver point of view. It describes eMMC (internal storage) device and SD (external storage) devices in details and SD protocol used for communicating with these devices in Linux.
With the HPE ProLiant DL325 Gen10 server, Hewlett Packard Enterprise is extending the worlds' most secure industry standard servers product families. This a secure and versatile single socket (1P) 1U AMD EPYC™ based platform offers an exceptional balance of processor, memory and I/O for virtualization and data intensive workloads. With up to 32 cores, up to 16 DIMMs, 2 TB memory capacity and support for up to 10 NVMe drives, this server delivers 2P performance with 1P economics.This datasheet includes features, port description, configuration guide and specification of this series.
An Introduction to eBPF (and cBPF). Topics covered include history, implementation, program types & maps. Also gives a brief introduction to XDP and DPDK
Lightelligence: Optical CXL Interconnect for Large Scale Memory PoolingMemory Fabric Forum
During the CXL Forum at OCP Global Summit, Lightelligence Director of Engineering Ron Swatzentruber provides an overview of the company's optical port expander products and test results.
eBPF is an exciting new technology that is poised to transform Linux performance engineering. eBPF enables users to dynamically and programatically trace any kernel or user space code path, safely and efficiently. However, understanding eBPF is not so simple. The goal of this talk is to give audiences a fundamental understanding of eBPF, how it interconnects existing Linux tracing technologies, and provides a powerful aplatform to solve any Linux performance problem.
During the CXL Forum at OCP Global Summit, MemVerge CEO Charles Fan presented accomplishments of the CXL industry since 2019, the development of concept cars occurring today, and his predictions for the future of CXL
The Linux kernel is undergoing the most fundamental architecture evolution in history and is becoming a microkernel. Why is the Linux kernel evolving into a microkernel? The potentially biggest fundamental change ever happening to the Linux kernel. This talk covers how companies like Facebook and Google use BPF to patch 0-day exploits, how BPF will change the way features are added to the kernel forever, and how BPF is introducing a new type of application deployment method for the Linux kernel.
Kubernetes Architecture - beyond a black box - Part 2Hao H. Zhang
This continues the Kubernetes architecture deep dive series. (Part 1 see https://www.slideshare.net/harryzhang735/kubernetes-beyond-a-black-box-part-1)
In Part 2 I'm going to cover the following:
- Kubernetes's 3 most import design choices: Micro-service Choreography, Level-Triggered Control, Generalized Workload and Centralized Controller
- Default scheduler limitation and community's next step
- Interface to production environment
- Workload abstraction: strength and limitations
This concludes my work and knowledge sharing about Kubernetes.
"Session ID: BUD17-400
Session Name: Secure Data Path with OPTEE - BUD17-400
Speaker: Mark Gregotski
Track: LHG
★ Session Summary ★
LHG is using the ION-based secure memory allocator integrated with OPTEE as the basis for secure data path processing pipeline. LHG is following the W3C EME protocol and supporting Content Decryption Modules (CDMs) from Widevine and PlayReady.
---------------------------------------------------
★ Resources ★
Event Page: http://connect.linaro.org/resource/bud17/bud17-400/
Presentation: https://www.slideshare.net/linaroorg/bud17400-secure-data-path-with-optee
Video: https://youtu.be/6JdzsWZq4Ls
---------------------------------------------------
★ Event Details ★
Linaro Connect Budapest 2017 (BUD17)
6-10 March 2017
Corinthia Hotel, Budapest,
Erzsébet krt. 43-49,
1073 Hungary
---------------------------------------------------
Keyword: LHG, secure-data, OPTEE
http://www.linaro.org
http://connect.linaro.org
---------------------------------------------------
Follow us on Social Media
https://www.facebook.com/LinaroOrg
https://twitter.com/linaroorg
https://www.youtube.com/user/linaroorg?sub_confirmation=1
https://www.linkedin.com/company/1026961"
Linux is usually at the edge of implementing new storage standards, and NVMe over Fabrics is no different in this regard. This presentation gives an overview of the Linux NVMe over Fabrics implementation on the host and target sides, highlighting how it influenced the design of the protocol by early prototyping feedback. It also tells how the lessons learned during developing the NVMe over Fabrics, and how they helped reshaping parts of the Linux kernel to support NVMe over Fabrics and other storage protocols better."
This presentation was delivered at LinuxCon Japan 2016 by Christoph Hellwig
It describes the MMC storage device driver functionality in Linux Kernel and it's role. It explains different type of storage devices available and how they are handled from MMC driver point of view. It describes eMMC (internal storage) device and SD (external storage) devices in details and SD protocol used for communicating with these devices in Linux.
With the HPE ProLiant DL325 Gen10 server, Hewlett Packard Enterprise is extending the worlds' most secure industry standard servers product families. This a secure and versatile single socket (1P) 1U AMD EPYC™ based platform offers an exceptional balance of processor, memory and I/O for virtualization and data intensive workloads. With up to 32 cores, up to 16 DIMMs, 2 TB memory capacity and support for up to 10 NVMe drives, this server delivers 2P performance with 1P economics.This datasheet includes features, port description, configuration guide and specification of this series.
Heterogeneous Computing : The Future of SystemsAnand Haridass
Charts from NITK-IBM Computer Systems Research Group (NCSRG)
- Dennard Scaling,Moore's Law, OpenPOWER, Storage Class Memory, FPGA, GPU, CAPI, OpenCAPI, nVidia nvlink, Google Microsoft Heterogeneous system usage
Yesterday's thinking may still believe NVMe (NVM Express) is in transition to a production ready solution. In this session, we will discuss how the evolution of NVMe is ready for production, the history and evolution of NVMe and the Linux stack to address where NVMe has progressed today to become the low latency, highly reliable database key value store mechanism that will drive the future of cloud expansion. Examples of protocol efficiencies and types of storage engines that are optimizing for NVMe will be discussed. Please join us for an exciting session where in-memory computing and persistence have evolved.
High-Density Top-Loading Storage for Cloud Scale Applications Rebekah Rodriguez
In this webinar, we will discuss how high-capacity Top-Loading Storage systems are being used for enterprise and cloud scale applications and will identify the key features of the modular architecture for use in today’s software defined storage (SDS) environments. - https://www.brighttalk.com/webcast/17278/527798
Using a Field Programmable Gate Array to Accelerate Application PerformanceOdinot Stanislas
Intel s'intéresse tout particulièrement aux FPGA et notamment au potentiel qu'ils apportent lorsque les ISV et développeurs ont des besoins très spécifiques en Génomique, traitement d'images, traitement de bases de données, et même dans le Cloud. Dans ce document vous aurez l'occasion d'en savoir plus sur notre stratégie, et sur un programme de recherche lancé par Intel et Altera impliquant des Xeon E5 équipés... de FPGA
Intel is looking at FPGA and what they bring to ISVs and developers and their very specific needs in genomics, image processing, databases, and even in the cloud. In this document you will have the opportunity to learn more about our strategy, and a research program initiated by Intel and Altera involving Xeon E5 with... FPGA inside.
Auteur(s)/Author(s):
P. K. Gupta, Director of Cloud Platform Technology, Intel Corporation
Hands-on Lab: How to Unleash Your Storage Performance by Using NVM Express™ B...Odinot Stanislas
(FR)
Voici un excellent document qui explique étape après étape comment installer, monitorer et surtout correctement benchmarker ses SSD PCIe/NVMe (pas si simple que ça). Autre élément clé : comment analyser la charge I/O de véritables applications? Combien d'IOPS, en read, en write, quelle bande passante et surtout quel impact sur la durée de vie des SSD? Bref à mettre en toute les mains, et un merci à mon collègue Andrey Kudryavtsev.
(EN)
An excellent content which describe step by step how to install, monitor and benchmark PCIe/NVMe SSD (many trick not so simple). Another key learning: how to measure real I/O activities on a real workload? How many R/W IOPS, block size, throughtput, and finally what's the impact on SSD endurance and (real)life? A must read, and a huge thanks to my colleague Andrey Kudryavtsev.
Auteurs/Authors:
Andrey Kudryavtsev, SSD Solution Architect, Intel Corporation
Zhdan Bybin, Application Engineer, Intel Corporation
Le SDN et NFV sont très à la mode en ce moment car en passant des appliance physiques aux équipement réseau massivement logiciel, celà devrait offrir une grande flexibilité et agilité aux entreprises (et telco en particulier). Néanmoins chainer des services réseau est un exercice encore très complexe et ce document vous explique ce qu'il est déjà possible de faire sur OpenStack en couplant par exemple : un load balancer (BigIP), un Firewall (BigIP), un réseau virtuel WAN (RiverBed) ou encore un routeur virtuel (Brocade).
Ceph: Open Source Storage Software Optimizations on Intel® Architecture for C...Odinot Stanislas
Après la petite intro sur le stockage distribué et la description de Ceph, Jian Zhang réalise dans cette présentation quelques benchmarks intéressants : tests séquentiels, tests random et surtout comparaison des résultats avant et après optimisations. Les paramètres de configuration touchés et optimisations (Large page numbers, Omap data sur un disque séparé, ...) apportent au minimum 2x de perf en plus.
SNIA : Swift Object Storage adding EC (Erasure Code)Odinot Stanislas
In depth presentation on EC integration in Swift object storage. Content delivered by Paul Luse, Sr. Staff Engineer @ Intel and Kevin Greenan, Staff Software Engineer - Box during fall SNIA event
Bare-metal, Docker Containers, and Virtualization: The Growing Choices for Cl...Odinot Stanislas
(FR)
Introduction très sympathique autour des environnements Cloud avec un focus particulier sur la virtualisation et les containers (Docker)
(ENG)
Friendly presentation about Cloud solutions with a focus on virtualization and containers (Docker).
Author: Nicholas Weaver – Principal Architect, Intel Corporation
Software Defined Storage - Open Framework and Intel® Architecture TechnologiesOdinot Stanislas
(FR)
Dans cette présentation vous aurez le plaisir d'y trouver une introduction plutôt détaillées sur la notion de "SDS Controller" qui est en résumé la couche applicative destinée à contrôler à terme toutes les technologies de stockage (SAN, NAS, stockage distribué sur disque, flash...) et chargée de les exposer aux orchestrateurs de Cloud et donc aux applications.
(ENG)
This presentation cover in detail the notion of "SDS Controller" which is in summary a software stack able to handle all storage technologies (SAN, NDA, distributed file systems on disk, flash...) and expose it to Cloud orchestrators and applications. Lots of good content.
Virtualizing the Network to enable a Software Defined Infrastructure (SDI)Odinot Stanislas
Une très intéressante présentation autour de la virtualisation des réseaux contenant des explications détaillées autour des VLAN, VXLAN, mais aussi d'NVGRE et surtout de GENEVE (Generic Network Virtualization Encapsulation) supporté pour la première fois sur la dernière carte 40 GbE d'Intel (XL710)
Intel développe une "ONP" (Open Network Platform) dit autrement un switch ouvert offrant les fonctions de base nécessaires au SDN. Si vous souhaitez connaitre le matériel utilisé, les stack logicielle exploitée et les compatibilité avec notamment les orchestrateurs, ce doc est fait pour vous.
Intel and Siveo wrote this content which explain how their Cloud Orchestrator is working. You will learn how to configure it, benefit from automatical workload placement feature and manage multiple hypervisors transparently.
Intel IT Open Cloud - What's under the Hood and How do we Drive it?Odinot Stanislas
L'IT d'Intel fait sa révolution et s'impose d'agir comme un "Cloud Service Provider". La transformation est initiée avec au programme la mise en place d'un Cloud Fédéré, Interopérable et Open mais aussi d'un framework de maturité, du DevOps et de la prise de risque. Bref, vraiment intéressant
Configuration and Deployment Guide For Memcached on Intel® ArchitectureOdinot Stanislas
This Configuration and Deployment Guide explores designing and building a Memcached infrastructure that is scalable, reliable, manageable and secure. The guide uses experience with real-world deployments as well as data from benchmark tests. Configuration guidelines on clusters of Intel® Xeon®- and Atom™-based servers take into account differing business scenarios and inform the various tradeoffs to accommodate different Service Level Agreement (SLA) requirements and Total Cost of Ownership (TCO) objectives.
Dans ce document vous trouverez les dernières améliorations faites sur OpenStack et comment certaines technologies Intel dopent la performance et la sécurité de l'environnement Cloud. Quelques exemple avec :
Comment créer des "pool" de VM sécurisées avec possibilité de géo tagging (technologies Intel présentent dans les serveurs HP, DELL, IBM… + Folsom, Nova, Horizon, Open Attestation)
Comment doper la sécurité du nouveau module de gestion des clés d'OpenStack (technologies Intel + Barbican)
Comment benchmarker le stockage object Swift avec COSBench (qui supporte maintenant Ceph, S3 et Amplidata)
Auteurs:
Girish Gopal - Strategic Planning, Intel Corporation
Malini Bhandaru - Security Architect, Intel Corporation
Scale-out Storage on Intel® Architecture Based Platforms: Characterizing and ...Odinot Stanislas
Issue du salon orienté développeurs d'Intel (l'IDF) voici une présentation plutôt sympa sur le stockage dit "scale out" avec une présentation des différents fournisseurs de solutions (slide 6) comprenant ceux qui font du mode fichier, bloc et objet. Puis du benchmark sur certains d'entre eux dont Swift, Ceph et GlusterFS.
Big Data and Intel® Intelligent Systems Solution for Intelligent transportationOdinot Stanislas
Explications sur comment il est possible d'utiliser la puissance d'Hadoop pour analyser les vidéos des caméras présentent sur les réseaux routiers avec pour objectif d'identifier l'état du trafic, le type de véhicule en déplacement et même l'usurpation de plaques d'immatriculation.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...
PCI Express* based Storage: Data Center NVM Express* Platform Topologies
1. PCI Express* based Storage: Data Center
NVM Express* Platform Topologies
Michael Hall
Director of Technology Solutions Enabling, Data Center Group, Intel Corporation
Jonmichael Hands
Technical Program Manager, Non-Volatile Memory Solutions Group, Intel Corporation
SSDS004
2. 2
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
3. 3
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
4. 4
PCI Express*and NVM Express*SSD Advantages Over SATA
Lower latency: Direct connection to CPU, increased CPU efficiency
Scalable performance:1 GB/s per lane –4 GB/s, 8 GB/s, … in one SSD
Industry standards: NVM Express*and PCI Express*(PCIe*) 3.0
Increased I/O: Up to 40 PCIelanes per CPU socket
Security protocols: Trusted Computing Group Opal
Low Power features: Low power link (L1.2), NVM Express*power states
Form factors: SFF-8639, SATA Express*, M.2, Add in card
Future: BGA (PCI-SIG), high density FF (SSD Form Factor WG)
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark*and MobileMark*, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.
5. 5
Form Factors for PCI Express*
Data Center
Client
SFF-8639
SATA Express
AIC
SFF-8639
SATA Express*
M.2
Add in Card
M.2
BGA
HD SSD FF
6. 6
80% increase in
Data Center SSD
revenue projected
SSD Market is Exploding
Source: Forward Insight and Intel
$0
$5
$10
$15
$20
2014
2017
SSD Market Billions $
Client
Data Center
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark*and MobileMark*, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.
7. 7
PCIeSSDs
are replacingSATA
in the Data Center
PCI Express*SSD Adoption in the Data Center
13%
17%
27%
32%
46%
53%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2013
2014
2015
2016
2017
2018
Data Center SSD Capacity (GB) by Interface
SATA
SAS
PCIe
PCI Express* (PCIe*)
Source: Forward Insight and Intel
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark*and MobileMark*, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.
8. 8
What do I need to start using an SSD?
PCI Express*support
Software and drivers
Infrastructure
9. 9
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
10. 10
Drive Connectors
SATA Signal Pins
Power and Control Pins
SATA
•Keyed only for SATA drives
•Separate power and data
Key
Signal Pins(port A)
Power and Control Pins
Signal Pins (Dual port, B)
SAS
•Backwards compatible with SATA
•Dual port
SFF-8639
•Supports SATA, SAS, and PCI Express* (PCIe*) x4 or two x2
•PCIedata, reference clock, and side band
SAS / SATA
Power and Control Pins
SAS
RefClk 0 & Lane 0
Lanes 1-3, SMBus, & Dual Port Enable
Refclk 1, 3.3V Aux, & Resets
11. 11
SATA Express*and SFF-8639 Comparison
SATAe
SFF-8639
SATA
Yes
Yes
PCIExpress*
x2
x2 or x4
Host Mux
Yes
No
Ref Clock
Optional
Required
EMI
SRIS
Shielding
Height
7mm
15mm
MaxPerformance
2 GB/s
4 GB/s
Bottom Line
Flexibility& Cost
Performance
SFF-8639 designed for data center, SATAedesigned for Client
Source: Seagate*(with permission)
12. 12
M.2 Form Factor Comparison
Host Socket 2
Host Socket 3
Device w/ B&M Slots
M.2 Socket 2
M.2 Socket 3
SATA
Yes, Shared
Yes, Shared
PCIex2
PCIex4
No
Yes
CommsSupport
Yes
No
Ref Clock
Required
Required
Max Performance
2 GB/s
4 GB/s
Bottom Line
Flexibility
Performance
M.2 Socket 3 is the best option for Data Center PCI Express*(PCIe*) SSDs
13. 13
Cabling Options for Data Center PCI Express*SSD Topologies
Reference Clock
PCIe Reset
SMBUS
miniSASHD cables lightly modified for PCI Express*(PCIe*)
Reference Clock
17. 17
Link Extension Devices –Switches and Retimers
Use Link Extension Devices for longer topologies
Retimer
PCIe3.0 x8 link
x8 link
PCIeSSD
x4link
Switch
PCI Express*(PCIe*) 3.0 x16 link
x32 link
PCIeSSD
x4link
Intel CPU
18. 18
Complex PCI Express*Topology –4 Connector
PCIe x16 slot
PCI Express* (PCIe*) Cable
Cabled Add in card with Link Extension
miniSASHD for PCIe
Backplane
SSD Drive Carrier
1
2
3
4
SFF-8639 Connector
19. 19
Complex PCI Express*Topology –5 Connector
PCIe x16 slot
PCIe Cable
Cabled Add in card with Link Extension
miniSASHD for PCIe
Backplane
SSD Drive Carrier
1
2
4
SFF-8639 Connector
PCI Express* (PCIe*) x16 Riser
3
5
20. 20
PCI Express*cabling for future topologies -OCuLink*
Category
OCuLink*
Standard Based
PCI-SIG
PCI Express* (PCIe*) Lanes
X4
Layout
Smaller footprint
Signal Integrity
Similaron loss dominated channels
PCIe4.0ready
16GT/s target
Clock, power
Supports clock and 3.3/5V power
Production Availability
Mid2015
12.85mm
2.83mm
Source:
OCuLinkinternal cables and connectors
21. 21
OCuLink*Provides Flexible Data Center Topologies
Board to board connections
Cabled add in card
Backplane
SFF-8639 Connector
PCI Express* (PCIe*) SSD
Source:
22. 22
Intel® Server Board S2600WT System with NVM Express*Support
Cabled PCIe 3.0 x16 AIC
SFF-8639
Backplane
miniSASHD for PCI Express*(PCIe*)
x16 Riser
miniSASHD for PCIe Cables
Drive
Carriers
2U Server
23. 23
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
24. 24
Industry goal is to get to the point where add in cards are today – they just work!
1.Physical Layer
•New fixtures required for SFF-8639
2.Configuration Space –no change
3.Link & Transaction Layer –no change
4.Platform Interop at Workshops
•Use adapters for M.2 and SFF-8639
PCI Express*Electrical Testing for SFF-8639
3.0 Compliance
25. 25
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
26. 26
What is required to support hot plug?
+
Server (Hardware + BIOS)
NVM Express*and PCI bus driver
SSD that supports unplanned power loss
27. 27
Hot AddHot Remove
Insert PCIeSSD Drive
BIOS configures PCI Express*(PCIe*) Port for Hot Plug
OS’s PCIeBus Driver setup
Hardware Presence detect
Vendor PCIeSSD Driver loaded
Storage Software & User determines usage
Drivers in known statePCIeSSD Drive inactive
Remove PCIeSSD Drive
BIOS configures PCIePort for Hot Plug
OS’s Disk driver disable, unloaded driver
Hardware Presence detect
Vendor PCIeSSD Driver – Failed LED
Storage Software or Driver determines Failure Replace
OS’s PCIeBus Driver cleanup
28. 28
Presence Detect
IO Timeout
Drive Active
Surprise Hot Remove
BIOS configures PCI Express*(PCIe*) Port for Hot Plug
Hardware Presence detect
Failed Access in Vendor PCIeSSD Driver
Storage SW or Driver determines Failure Replace
OS’s PCIeBus disable, unload driver
IO timeout in Vendor PCIeSSD Driver
Race
Master Abort
OS’s PCIeBus Driver cleanup
Remove PCIeSSD Drive
29. 29
Agenda
•PCI Express*SSD Data Center Ecosystem –what is the opportunity?
•Platform topology options
•Validation tools and methodologies
•Hot plug support for Intel® Xeon® processor based servers
•Upcoming workshops
30. 3020132014Q1Q2Q3Q4Q1Q2Q3Q4
NVM Express* (NVMe) Community IDF
NVM Express Community IDF
SFF 8639 Spec
Platform testing Taiwan
Platform testing
US and Taiwan
Non-Sig Compliance boards available
SFF-8639
Plugfest#1
UNH NVMePlugfest#1
UNH NVMePlugfest#2
UNH NVMePlugfest#3
Nov 2014
First PCI Express* 3.0 Integrators list
Testing Events
PCI-SIG and Compliance
NVMeCommunities at IDF
Form Factor
PCI Express*Ecosystem Workshops and Plugfests
NVMePlugfests
UNH –University of New Hampshire
31. 31
•NVM Express*(NVMe) Solid-State Drives are going to become pervasive in the data center
•Intel is accelerating the ecosystem to make it easier to deploy complex PCI Express*(PCIe*) SSD topologies with Intel® Xeon® processor based platforms
•PCIeprovides multiple form factors and flexible topologies for designing into servers and market segments with different requirements
•Start designing new PCI Express form factors into servers to take full advantage of NVMe!
Summary
32. 32
•Design servers to support PCI Express*(PCIe*) Solid-State Drives to take advantage of the performance and efficiency of NVM Express*(NVMe) SSDs
•Get involved with NVMeat www.nvmexpress.organd participate with PCI-SIG at www.pcisig.comfor developments of new storage technology
•See your Intel representative for more information about what Intel is doing to accelerate PCIeSSDs in the data center
•Participate in industry events to advance the PCIeecosystem to support new form factors and topologies
Next Steps
33. 33
A PDF of this presentation is available from our Technical Session Catalog: www.intel.com/idfsessionsSF. This URL is also printed on the top of Session Agenda Pages in the Pocket Guide.
Demos in the showcase –Booths #175 and #259
Additional info in the NVM Express*community –Booths #161-178
More web based info: www.intel.comssd
Additional Sources of Information
35. 35
Risk Factors
The above statements and any others in this document that refer to plans and expectations for the second quarter, the year and the future are forward- looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “plans,”“believes,” “seeks,” “estimates,” “may,” “will,” “should” and their variations identify forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Many factors could affect Intel’s actual results, and variances from Intel’s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be important factors that could cause actual results to differ materially from thecompany’s expectations. Demand for Intel's products is highly variable and, in recent years, Intel has experienced declining orders in the traditional PC market segment. Demand could be different from Intel's expectations due to factors including changes in business and economic conditions; consumer confidence or income levels; customer acceptance of Intel’s and competitors’ products; competitive and pricing pressures, including actions taken by competitors; supply constraints and other disruptions affecting customers; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Intel operates in highly competitive industries and its operations have high costs that are either fixedor difficult to reduce in the short term. Intel's gross margin percentage could vary significantly from expectations based on capacity utilization; variationsin inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; segment product mix; the timing and execution of the manufacturing ramp and associated costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; and product manufacturing quality/yields. Variations in gross margin may also be caused by the timing of Intel product introductions and related expenses, including marketing expenses, and Intel's ability to respond quickly to technological developments and to introduce new products or incorporate new features into existing products, which may result in restructuring and asset impairment charges. Intel's resultscould be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel’s results could be affected by the timing of closing of acquisitions, divestitures and other significant transactions. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust, disclosure and other issues, such as the litigation and regulatory matters described in Intel's SEC filings. An unfavorable ruling could include monetary damages or an injunction prohibiting Intel from manufacturing or selling one or more products, precluding particular business practices, impacting Intel’s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’sSEC filings, including the company’s most recent reports on Form 10-Q, Form 10-K and earnings release.
Rev. 4/15/14
37. 37
PCI Express*(PCIe*) Switches and Retimers
PCI Express*(PCIe*) Switches
•User configurable lane distribution
•Ease of implementation and hotplugsupport
•Less BIOS development needed
•Slot configurability
•Acts like PCIeHBA
•Extra software features
•Switches available from Avago*– PLX at www.plxtech.com
PCIeRetimers
•Channel has > -20db loss: at 8GT/s PCIe 3.0
•Intel co-authored ECN spec in PCI-SIG
•Retimersavailable from www.IDT.com
Definitions
•Repeater: A Retimeror a Re-driver
•Re-driver: Analog and not protocol aware
Retimer: Physical Layer protocol aware, software transparent, Extension Device. Forms two separate electrical sub-links.
38. 38
PCI Express*Hot Plug: Supported on Intel® Xeon® Processor Based Servers
Terminology
•Hot Plug: general term to describe adding and removing devices while system is running
•Hot Add –Also known as Hot Insertion
•Hot Removal –Software Managed Hot Removal (orderly)
•Surprise Hot Removal –possible outstanding IO transactions
•Hot Swap (Hot Add + Removal)
Requirements for Surprise Removal
•Hardware: registers and drive status, master abort, and disable link
•Software: PCI Bus Driver and NVM Express*Driver
•Drive: Support unplanned power loss
•LER, DPC, eDPC–not required but make it easier to validate
39. 39
Hot Plug Requirements –System
•PCI Express*(PCIe*) Slot Capability register: Hot Plug Capableand Hot Plug Surprise
•PCIeSlot Status: Presence Change Interruptto notify PCIebus driver
•Backplane, pre-charge circuit to limit in- rush current, isolated Reset, Refclk, and Smbus, presence detect via IfDet# (pin 4) and PRSNT# (pin10)
•Drive Identifyand FailIndicators
•PCIeLink Down Interrupt –for link down, uses PCIeAER
•BIOS: UEFI 2.3.1 or later, pre-allocate memory resources
•Pre-allocate slot resources (Bus IDs, interrupts, memory regions) using ACPI tables