SlideShare a Scribd company logo
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 2
Universal Asynchronous Receive and transmit IP core
Aneesh Raveendran
aneeshr2020@gmail.com
ER&DCI Institute of Technology,
Centre for Development of Advanced Computing(C-DAC),
Thiruvananthapuram, Kerala
CHAPTER 2
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 3
INTRODUCTION
The RS-232 serial communication protocol is a standard protocol used in asynchronous serial
communication. It is a primary protocol used over modem line. It is used for connecting DTE
(Data Terminal Equipment) and DCE (Data Circuit terminating Equipment).The protocol was
standardised by EIA (Electronic Industry Association). The standard defines the electrical
characteristics, timing of signals, the meaning of signals, the physical size and pin out of
connectors.
RS232 physical properties:
The RS232 standard describes a communication method capable of communicating in
different environments. This has had its impact on the maximum allowable voltages etc. on
the pins. The maximum baud rate defined for example is 20 kbps. With current devices like
the 16550A UART, maximum speeds of 1.5 Mbps are allowed.
Voltages:
The signal level of the RS232 pins can have two states. A high bit, or mark state is identified
by a negative voltage and a low bit or space state uses a positive value. This might be a bit
confusing, because in normal circumstances, high logical values are defined by high voltages
also. The voltage limits are shown below.
Level
Transmitter
capable (V)
Receiver
capable (V)
Space state (0) +5 ... +15 +3 ... +25
Mark state (1) -5 ... -15 -3 ... -25
Undefined - -3 ... +3
Table 1: RS232 voltage values
NOTE:
Despite the high voltages present, it is not possible to destroy the serial port by short circuiting. Only
applying external voltages with high currents may eventually burn out the driver chips. Still then, the
UART won't be damaged in most cases.
Maximum cable length:
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 4
The maximum cable length is 50 feet, or the cable length equal to a capacitance of 2500 pF.
This means that using a cable with low capacitance allows you to span longer distances
without going beyond the limitations of the standard. If for example UTP CAT-5 cable is
used with a typical capacitance of 17 pF/ft, the maximum allowed cable length is 147 feet.
The cable length mentioned in the standard allows maximum communication speed to occur.
If speed is reduced by a factor 2 or 4, the maximum length increases dramatically. Texas
Instruments has done some practical experiments years ago at different baud rates to test the
maximum allowed cable lengths. Keep in mind, that the RS232 standard was originally
developed for 20 kbps. By halving the maximum communication speed, the allowed cable
length increases a factor ten.
Baud rate Maximum cable length (ft)
19200 50
9600 500
4800 1000
2400 3000
Table 2: RS232 cable length according to Texas Instruments
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 5
FRAME FORMAT
A frame is a complete and non-divisible packet of bits. A frame includes both information
(e.g., data and characters) and overhead (e.g., start bit, error checking and stop bits). In
asynchronous serial protocols such as RS-232, the frame consists of one start bit, seven or
eight data bits, parity bits, and stop bits. A timing diagram for an RS-232 frame consisting of
one start bit, 7 data bits, one parity bits and two stop bits is shown below in figure.
Fig 2 : RS-232 Frame (1 start bit, 7 data bits, 1 parity bits, and 2 stop bits)
The start bit is used to signal the beginning of a frame and the stop bit is used to signal the
end of a frame. Parity is used to detect transmission errors. For even parity checking, the
number of 1's in the data plus the parity bit must equal an even number. For odd parity, this
sum must be an odd number. Parity bits are used to detect errors in transmitted data. Before
sending out a frame, the transmitter sets the parity bit so that the frame has either even or odd
parity. The receiver and transmitter have already agreed upon which type of parity check
(even or odd) is being used. When the frame is received, then the receiver checks the parity
of the received frame. If the parity is wrong, then the receiver knows an error occurred in
transmission and the receiver can request that the transmitter re-send the frame.
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 6
CHAPTER 3
SERIAL COMMUNICATION
Serial communication is the process of sending data one bit at a time, sequentially, over a
communication channel or computer bus. Figure shows the relationship between the various
components in a serial link. These components are the UART, the serial channel, and the
interface logic. An interface chip known as the universal asynchronous
receiver/transmitter or UART is used to implement serial data transmission. The UART sits
between the host computer and the serial channel.
Fig 3: Asynchronous (RS-232) serial link
The serial communication link mainly consisting of three components,
UART
LEVEL SHIFTER
RS232 CONNECTOR
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 7
CHAPTER 4
DESIGN SPECIFICATION
Fig 4: Top level entity-IP core
NAME DESCRIPTION
CONNECTOR 9-PIN
START BIT 1
DATA BIT 8
PARITY BIT NONE
STOP BIT 1
BAUD RATE 1200,2400,4800,9600,19200,38400,57600,
115200
DEFAULT BAUD RATE 9600
Table 3: Design specification
TXINT
DATA_IN
N
BRR
TDRE
EN
SCLK
UART
RXD
TXD
RXINT
RDRF
DATA_OUT
RST
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 8
CHAPTER 5
UART-Universal Asynchronous Receiver/Transmitter
It is a type of "asynchronous receiver/transmitter". UART is a piece of hardware that
translates data between parallel and serial forms. UARTs are commonly used in conjunction
with communication standards such as EIA RS-232, RS-422 or RS-485. The universal
designation indicates that the data format and transmission speeds are configurable and that
the actual electric signalling levels and methods (such as differential signalling etc.) typically
are handled by a special driver circuit external to the UART.
8 1 TXD
ENABLE
SCLK
BRR
DA A 8 1 RXDDATA_OUT
8
8 Uart
Transmitter
Baud
Rate
Generator
Uart
Receiver
Control Reg.
DATA_IN
8
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 9
Fig 5: General block diagram of UART
CHAPTER 6
UART TRANSMITTER
UART transmitter converts parallel data into serial data. It accepts 8-bit input data from the
data bus or processor and converts it into serial data. The top level entity of UART
transmitter is shown below
8
EN
TDRE TXD
TXINT
Fig 6: Top level entity of UART Transmitter
The UART transmitter accepts the 8-bit data through Data_in and performs the
serializing action on the input data. The microprocessor can write the data into
Data_in, only by checking the TDRE (Transmit Data Register Empty) pin. Logic 1 on
TDRE represents the Transmit data register is empty and the transmission is possible,
otherwise transmission is not possible. After the completion of the transmission the
UART transmitter produces Transmission complete interrupt (TXINT).The UART
transmitter is working on the clock produce by the Baud rate generator.
The uart transmitter is only active when a high input signal is in the Enable pin.
UART
TRANSMITTER
DATA_IN
BCLK
RST
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 10
SERIALIZER
BCLK
TDRE TXD
TXINT
EN
RST
SCSR
SERIALIZER
Fig 7: Internal diagram-UART Transmitter
SIGNAL EXPANSION LENGTH
EN Enable 1
BCLK Baud Rate Clock 1
DATA_IN Input Data 8
RST System Reset 1
TDR (8) TSR (10)
TRANSMIT
CONTROL
6 5 4 3 2 1 0TDRE
DATA_IN 8
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 11
SCSR Serial Control Status Register 8
TDR Transmit Data Register 8
TDRE Transmit Data Register Empty 1
TSR Transmit Shift Register 10
TXD Transmit Data 1
TXINT Transmission complete Interrupt 1
Table 4: Signals in UART Transmitter
SM CHART FOR UART TRAMSMITTER
0 -- state
--operation
1
--condition
0
1
0 1
RESET
bclk
IDLE
TDRE
TDR Data_in
set TDRE
form TSR
SYNCH
bclk clear TSR(0)
TXDATA
EN=1
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 12
0 1
CHAPTER 7
UART RECEIVER
UART receiver converts serial data into parallel data. It performs the de-serializing action on
the input data. The top level entity of UART receiver is shown below
8
EN
RDRF
RXINT RXD
BCLK
RST
Fig 8: Top level entity-UART Receiver
It accepts set of single bits from the input and converts it into a parallel (8-bit) data. The
received data is given to the processor data bus. The processor can read the data from
Receive Data Register (RDR), only the Receive Data Register is full (RDRF). Once the
bclk
Tcnt=9Set TXINT
Clear Tcnt
Reset TDRE
TXD TSR(Tcnt)
inc Tcnt
UART
RECEIVER
DATA_OUT
BCLKx8
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 13
RSR (10)
Receive Data register is full, the UART controller make the pin RDRF (Receive Data
Register Full) high. Once the reception is completed the UART controller generates a
Reception complete interrupt (RXINT).
The bit stream coming from the RXD pin is not synchronized with the clock (bclk). If we
attempt to read the RXD at the rising edge of bclk we would have a problem if RXD changed
near the clock edge. And also we would have a setup and hold time problems. To ensure the
start bit an oversampling procedure is used. The uart receiver is active only when a high input
signal is applied to EN pin.
RXD start bit 1st
data bit 2nd
data bit
* * *
BCLKx8
Fig 9: Oversampling
DE-SERIALIZER
EN
RDRF RXD
RXINT
BCLK
BCLKx8
RECEIVE
CONTROL
BCLK
DATA_OUT 8
RSR (10)RDR (8)
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 14
RST
SCSR
Fig 10: Internal diagram-UART Receiver
SM CHART FOR UART RECEIVER
1 0
0
1
RDRF 5 4 3 2 1 07
RESET
clk
IDLE
RXD
START_DETECT
clkx8
RXDClear cnt1
R
EN=1
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 15
1 0
1 0
(Contd…………..)
0 1
Cnt1=3 Inc cnt1Clear cnt1
X
x
RXDATA
clkx8
Inc cnt1
cnt1=7
Cnt2=8
Shift RSR
Inc cnt2
Clear cnt1
R
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 16
0
1
0 1
CHAPTER 8
BAUD RATE GENERATOR
In telecommunications and electronics, baud is synonymous to symbols per second or pulses
per second. It is the unit of symbol rate, also known as baud rate or modulation rate; the
number of distinct symbol changes (signalling events) made to the transmission medium per
second in a digitally modulated signal or a line code. The baud rate is used for the
communication purpose and it is used to identify that how much of the data had been
transferred but at how much speed.
The top level entity is shown below,
BRR
BCLK
SCLK
RST
Fig 11: Top Level Entity- Baud Rate Generator
8
EN
RDR RSR
Generate TXINT
Set RDRF
Clr cnt1
Clr cnt2
clk
INTERUPT
BAUD RATE
GENERATOR
BCLKx8
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 17
The baud rate generator generates the clock signal according to the baud rate Register (BRR).
The below table shows the different baud rate register and the Baud rate that we used in our design.
Baud Rate Register Baud Rate
00000011 1200
00000001 2400
00000010 4800
00000000 9600
00000100 19200
00000101 38400
00000110 57600
00000111 115200
Table 5: Baud Rate Register and Baud Rate
CHAPTER 9
SIMULATION RESULTS
Fig 12: UART Transmitter
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 18
Fig 13: UART Receiver
Fig 14: Baud Rate Generator
CHAPTER 10
SYNTHESIS
The UART IP core is synthesized using ALTERA QUARTUS II version 11.0 for ALTERA
Stratix FPGA series number EP2S15F672C3. The total device utilization of uart IP core for
above series is shown in Fig15.
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 19
Fig15: Device Utilization of UART IP core
Fig 16: Maximum Frequency of UART IP core
Figure 16 shows the maximum frequency supported by the FPGA. The table 6 shows the
summary of the device utilization of UART IP core.
PARAMETER USAGE PERCENTAGE
Logic Utilization 1%
Combinational ALUTs 151/12480 1%
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 20
Dedicated Logic Registers 87/12480 1%
Total Registers 83 0%
Total Pins 33/367 9%
Total PLL and DLL 0 0%
Max. Frequency 396.1MHz
Table 6: Device Utilization -Summary
The figure 17 shows the Register Transfer Level (RTL) view of the UART IP core. It consists
of the RTL view of uart Transmitter, receiver and baud rate generator.
Fig 17: RTL View –Top Level entity
Figure 18 shows the hardware representation of baud rate generator, Fig 19 represents the
hardware representation of uart Receiver, and Fig 20 represents the implementation of state
diagram used for UART Receiver in ALTERA QUARTUS II.
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 21
Fig 18: Hadware Representation-Baud Rate Generator
Fig 19: : Hadware Representation-UART Receiver
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 22
Fig 20: State Diagram in UART Receiver by ALTERA
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 23
Fig 21: Hadware Representation-UART Transmitter
CHAPTER 11
TESTING-UART
The UART IP core is tested using ALTERA STRATIX FPGA series number EP2S15F672C3
and a Personal Computer. The synthesised netlist is downloaded into the FPGA and ready for
testing. The testing structure of the IP core is divided into three phases.
Phase 1: Transmitter testing
The transmitter is tested by placing a random data in DATA_IN pin of the transmitter and a
baud rate generator into the FPGA. After the successful implementation of Transmitter IP
core in the FPGA, then connect the FPGA board into the personal computer. The steps for
transmitter testing are listed below.
1) Place a random data in DATA_IN pin of the UART transmitter.
2) Fix the Baud Rate for transmission
3) Synthesis and download the netlist into the FPGA
4) Connect the FPGA board into the Personal Computer
5) Establish a connection between the FPGA board and Personal Computer using a
Hyper Terminal
6) After the successful connection establishment Press RESET signal in FPGA
7) The stored data is printed in the Hyper Terminal; if this data is matched with stored
data then UART transmitter is working correctly
8) Repeat the above steps for various data and baud rates
Phase 2: Receiver testing
The UART receiver is tested by sending an 8 bit of serial data through RXD pin. The receiver
is tested by downloading uart receiver and a baud rate generator circuit. The steps used are
listed below.
1) Fix the Baud Rate for transmission
2) Synthesis and download the netlist into the FPGA
3) Connect the FPGA board into the Personal Computer
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 24
4) Establish a connection between the FPGA board and Personal Computer using a
Hyper Terminal
5) send a character through Hyper Terminal using a key board
6) If the data is received successfully in the FPGA then a LED of FPGA will be glow
7) Repeat the above steps for various data and baud rates
Phase 3: UART IP core testing
The entire UART IP core is tested using a loop back structure. Figure 22 shows the UART
testing structure.
Fig 22: Loop Back Structure
The steps used for UART IP core testing is shown is below.
1) Fix the Baud Rate for transmission
2) Synthesis and download the netlist into the FPGA
3) Connect the FPGA board into the Personal Computer
4) Establish a connection between the FPGA board and Personal Computer using a
Hyper Terminal
5) send a character through Hyper Terminal using a key board
6) Checks the receiver section of the Hyper Terminal, if the received data is matched
with the transmitted data, then the UART IP core is working properly.
7) Repeat the above steps with different baud rates.
Fig 23 shows the test result of UART transmitter with character ‘ A’ at baud rate 115200Hz.
Fig 24 shows the test result of UART transmitter with character ‘ AF’ at baud rate 1200Hz.
Fig 25 shows the test result of entire UART IP core at baud rate 115200Hz.
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 25
Fig23: Transmitting ‘A’ at 1115200 Hz
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 26
Fig24: Transmitting ‘AF’ at 1200 Hz
Universal Asynchronous Receive and Transmit IP core
ER & DCI-IT, CDAC TVM Page 27
Fig 25: UART at 115200 Hz

More Related Content

What's hot

Serial Communication
Serial CommunicationSerial Communication
Serial Communication
UshaRani289
 
Mridul_Verma_Intern_Tech_Adityaa_UART
Mridul_Verma_Intern_Tech_Adityaa_UARTMridul_Verma_Intern_Tech_Adityaa_UART
Mridul_Verma_Intern_Tech_Adityaa_UART
Mridul Verma
 
8051 serial communication-UART
8051 serial communication-UART8051 serial communication-UART
8051 serial communication-UART
Pantech ProLabs India Pvt Ltd
 
Uart driver nov13
Uart driver nov13Uart driver nov13
Uart driver nov13
abinaya m
 
Serial Communication Part-16
Serial Communication Part-16Serial Communication Part-16
Serial Communication Part-16
Techvilla
 
Ju2416921695
Ju2416921695Ju2416921695
Ju2416921695
IJERA Editor
 
UART
UARTUART
Uart
UartUart
UART
UARTUART
Data comm 2 latest
Data comm 2 latestData comm 2 latest
Data comm 2 latest
Rohit Nair
 
Design and implementation of uart on soc
Design and implementation of uart on socDesign and implementation of uart on soc
Design and implementation of uart on soc
Ijrdt Journal
 
Universal Serial Communication Interface
Universal Serial Communication InterfaceUniversal Serial Communication Interface
Universal Serial Communication Interface
Sandesh Agrawal
 
KYL 210 RF Module user manual
KYL 210 RF Module user manualKYL 210 RF Module user manual
KYL 210 RF Module user manual
Sunny Zhou
 
Rs 232 interface
Rs 232 interfaceRs 232 interface
Rs 232 interface
PREMAL GAJJAR
 
rs-232
rs-232rs-232
8251
82518251
8251
Aisu
 
I2C
I2CI2C
Verification of uart ip core using uvm
Verification of uart ip core using uvmVerification of uart ip core using uvm
Verification of uart ip core using uvm
eSAT Publishing House
 
Uart
UartUart

What's hot (19)

Serial Communication
Serial CommunicationSerial Communication
Serial Communication
 
Mridul_Verma_Intern_Tech_Adityaa_UART
Mridul_Verma_Intern_Tech_Adityaa_UARTMridul_Verma_Intern_Tech_Adityaa_UART
Mridul_Verma_Intern_Tech_Adityaa_UART
 
8051 serial communication-UART
8051 serial communication-UART8051 serial communication-UART
8051 serial communication-UART
 
Uart driver nov13
Uart driver nov13Uart driver nov13
Uart driver nov13
 
Serial Communication Part-16
Serial Communication Part-16Serial Communication Part-16
Serial Communication Part-16
 
Ju2416921695
Ju2416921695Ju2416921695
Ju2416921695
 
UART
UARTUART
UART
 
Uart
UartUart
Uart
 
UART
UARTUART
UART
 
Data comm 2 latest
Data comm 2 latestData comm 2 latest
Data comm 2 latest
 
Design and implementation of uart on soc
Design and implementation of uart on socDesign and implementation of uart on soc
Design and implementation of uart on soc
 
Universal Serial Communication Interface
Universal Serial Communication InterfaceUniversal Serial Communication Interface
Universal Serial Communication Interface
 
KYL 210 RF Module user manual
KYL 210 RF Module user manualKYL 210 RF Module user manual
KYL 210 RF Module user manual
 
Rs 232 interface
Rs 232 interfaceRs 232 interface
Rs 232 interface
 
rs-232
rs-232rs-232
rs-232
 
8251
82518251
8251
 
I2C
I2CI2C
I2C
 
Verification of uart ip core using uvm
Verification of uart ip core using uvmVerification of uart ip core using uvm
Verification of uart ip core using uvm
 
Uart
UartUart
Uart
 

Viewers also liked

Evaluation Question 1
Evaluation Question 1Evaluation Question 1
Evaluation Question 1
LydiaGreenwood
 
25 Important Content Marketing Statistics
25 Important Content Marketing Statistics25 Important Content Marketing Statistics
25 Important Content Marketing Statistics
The Content Strategist
 
Evaluation Question 1: In what ways does your media product use, develop or c...
Evaluation Question 1: In what ways does your media product use, develop or c...Evaluation Question 1: In what ways does your media product use, develop or c...
Evaluation Question 1: In what ways does your media product use, develop or c...
LydiaGreenwood
 
Singapore
Singapore Singapore
Singapore
zoolainsudan
 
ISE FundHub product guide
ISE FundHub product guideISE FundHub product guide
ISE FundHub product guide
gerrysugrue
 
Unalligned versus natureally alligned memory access
Unalligned versus natureally alligned memory accessUnalligned versus natureally alligned memory access
Unalligned versus natureally alligned memory access
Aneesh Raveendran
 
Transforming learning with new technologies
Transforming learning with new technologiesTransforming learning with new technologies
Transforming learning with new technologies
tonikaperry
 
Resources Valley
Resources ValleyResources Valley
Resources Valley
Resources Valley
 
Architecture and Implementation of the ARM Cortex-A8 Microprocessor
Architecture and Implementation of the ARM Cortex-A8 MicroprocessorArchitecture and Implementation of the ARM Cortex-A8 Microprocessor
Architecture and Implementation of the ARM Cortex-A8 Microprocessor
Aneesh Raveendran
 
Design of FPGA based 8-bit RISC Controller IP core using VHDL
Design of FPGA based 8-bit RISC Controller IP core using VHDLDesign of FPGA based 8-bit RISC Controller IP core using VHDL
Design of FPGA based 8-bit RISC Controller IP core using VHDL
Aneesh Raveendran
 
Reversible Logic Gate
Reversible Logic GateReversible Logic Gate
Reversible Logic Gate
Aneesh Raveendran
 

Viewers also liked (11)

Evaluation Question 1
Evaluation Question 1Evaluation Question 1
Evaluation Question 1
 
25 Important Content Marketing Statistics
25 Important Content Marketing Statistics25 Important Content Marketing Statistics
25 Important Content Marketing Statistics
 
Evaluation Question 1: In what ways does your media product use, develop or c...
Evaluation Question 1: In what ways does your media product use, develop or c...Evaluation Question 1: In what ways does your media product use, develop or c...
Evaluation Question 1: In what ways does your media product use, develop or c...
 
Singapore
Singapore Singapore
Singapore
 
ISE FundHub product guide
ISE FundHub product guideISE FundHub product guide
ISE FundHub product guide
 
Unalligned versus natureally alligned memory access
Unalligned versus natureally alligned memory accessUnalligned versus natureally alligned memory access
Unalligned versus natureally alligned memory access
 
Transforming learning with new technologies
Transforming learning with new technologiesTransforming learning with new technologies
Transforming learning with new technologies
 
Resources Valley
Resources ValleyResources Valley
Resources Valley
 
Architecture and Implementation of the ARM Cortex-A8 Microprocessor
Architecture and Implementation of the ARM Cortex-A8 MicroprocessorArchitecture and Implementation of the ARM Cortex-A8 Microprocessor
Architecture and Implementation of the ARM Cortex-A8 Microprocessor
 
Design of FPGA based 8-bit RISC Controller IP core using VHDL
Design of FPGA based 8-bit RISC Controller IP core using VHDLDesign of FPGA based 8-bit RISC Controller IP core using VHDL
Design of FPGA based 8-bit RISC Controller IP core using VHDL
 
Reversible Logic Gate
Reversible Logic GateReversible Logic Gate
Reversible Logic Gate
 

Similar to Universal Asynchronous Receive and transmit IP core

UART Serial Communication Module Design and Simulation Based on VHDL
UART Serial Communication Module Design and Simulation Based on VHDLUART Serial Communication Module Design and Simulation Based on VHDL
UART Serial Communication Module Design and Simulation Based on VHDL
IJERA Editor
 
Synthesis & FPGA Implementation of UART IP Soft Core
Synthesis & FPGA Implementation of UART IP Soft CoreSynthesis & FPGA Implementation of UART IP Soft Core
Synthesis & FPGA Implementation of UART IP Soft Core
ijsrd.com
 
serial-200505101453.pdf
serial-200505101453.pdfserial-200505101453.pdf
serial-200505101453.pdf
KiranG731731
 
Ec8791 lpc2148 uart
Ec8791 lpc2148 uartEc8791 lpc2148 uart
Ec8791 lpc2148 uart
RajalakshmiSermadurai
 
Serial Communication Interface with Error Detection
Serial Communication Interface with Error DetectionSerial Communication Interface with Error Detection
Serial Communication Interface with Error Detection
iosrjce
 
M010617376
M010617376M010617376
M010617376
IOSR Journals
 
Firmware implementation of UART using Bare metal programming
Firmware implementation of UART using Bare metal programmingFirmware implementation of UART using Bare metal programming
Firmware implementation of UART using Bare metal programming
IRJET Journal
 
Serial Port Device Driver
Serial Port Device DriverSerial Port Device Driver
Serial Port Device Driver
Emblogic
 
Implementation of Universal Asynchronous Receiver and Transmitter
Implementation of Universal Asynchronous Receiver and TransmitterImplementation of Universal Asynchronous Receiver and Transmitter
Implementation of Universal Asynchronous Receiver and Transmitter
IJERA Editor
 
Hands On Data Communications, Networking and TCP/IP Troubleshooting
Hands On Data Communications, Networking and TCP/IP TroubleshootingHands On Data Communications, Networking and TCP/IP Troubleshooting
Hands On Data Communications, Networking and TCP/IP Troubleshooting
Living Online
 
RFID Based Toll Gate System
RFID Based Toll Gate SystemRFID Based Toll Gate System
RFID Based Toll Gate System
Ameer Khan
 
Tutorial
TutorialTutorial
Tutorial
ROBOTZLABZ
 
Embedded real time-systems communication
Embedded real time-systems communicationEmbedded real time-systems communication
Embedded real time-systems communication
Vijay Kumar
 
Rs 232 & usb ieee1394 communication
Rs 232 & usb  ieee1394 communicationRs 232 & usb  ieee1394 communication
Rs 232 & usb ieee1394 communication
Vijay Kumar
 
AN INTRODUCTION TO SERIAL PORT INTERFACING
AN INTRODUCTION TO SERIAL PORT INTERFACINGAN INTRODUCTION TO SERIAL PORT INTERFACING
AN INTRODUCTION TO SERIAL PORT INTERFACING
Total Project Solutions
 
Serial Communication Uart soc
Serial Communication  Uart socSerial Communication  Uart soc
Serial Communication Uart soc
Satyam Sharma
 
INTERFACING WITH INTEL 8251A (USART)
INTERFACING WITH INTEL 8251A (USART)INTERFACING WITH INTEL 8251A (USART)
INTERFACING WITH INTEL 8251A (USART)
Prof Ansari
 
4 ql uart_psb_ds_revc
4 ql uart_psb_ds_revc4 ql uart_psb_ds_revc
4 ql uart_psb_ds_revc
Doped Maverick
 
Uart wiki
Uart wikiUart wiki
Uart wiki
pankajchokadi
 
Chapter5
Chapter5Chapter5
Chapter5
Bisrat Girma
 

Similar to Universal Asynchronous Receive and transmit IP core (20)

UART Serial Communication Module Design and Simulation Based on VHDL
UART Serial Communication Module Design and Simulation Based on VHDLUART Serial Communication Module Design and Simulation Based on VHDL
UART Serial Communication Module Design and Simulation Based on VHDL
 
Synthesis & FPGA Implementation of UART IP Soft Core
Synthesis & FPGA Implementation of UART IP Soft CoreSynthesis & FPGA Implementation of UART IP Soft Core
Synthesis & FPGA Implementation of UART IP Soft Core
 
serial-200505101453.pdf
serial-200505101453.pdfserial-200505101453.pdf
serial-200505101453.pdf
 
Ec8791 lpc2148 uart
Ec8791 lpc2148 uartEc8791 lpc2148 uart
Ec8791 lpc2148 uart
 
Serial Communication Interface with Error Detection
Serial Communication Interface with Error DetectionSerial Communication Interface with Error Detection
Serial Communication Interface with Error Detection
 
M010617376
M010617376M010617376
M010617376
 
Firmware implementation of UART using Bare metal programming
Firmware implementation of UART using Bare metal programmingFirmware implementation of UART using Bare metal programming
Firmware implementation of UART using Bare metal programming
 
Serial Port Device Driver
Serial Port Device DriverSerial Port Device Driver
Serial Port Device Driver
 
Implementation of Universal Asynchronous Receiver and Transmitter
Implementation of Universal Asynchronous Receiver and TransmitterImplementation of Universal Asynchronous Receiver and Transmitter
Implementation of Universal Asynchronous Receiver and Transmitter
 
Hands On Data Communications, Networking and TCP/IP Troubleshooting
Hands On Data Communications, Networking and TCP/IP TroubleshootingHands On Data Communications, Networking and TCP/IP Troubleshooting
Hands On Data Communications, Networking and TCP/IP Troubleshooting
 
RFID Based Toll Gate System
RFID Based Toll Gate SystemRFID Based Toll Gate System
RFID Based Toll Gate System
 
Tutorial
TutorialTutorial
Tutorial
 
Embedded real time-systems communication
Embedded real time-systems communicationEmbedded real time-systems communication
Embedded real time-systems communication
 
Rs 232 & usb ieee1394 communication
Rs 232 & usb  ieee1394 communicationRs 232 & usb  ieee1394 communication
Rs 232 & usb ieee1394 communication
 
AN INTRODUCTION TO SERIAL PORT INTERFACING
AN INTRODUCTION TO SERIAL PORT INTERFACINGAN INTRODUCTION TO SERIAL PORT INTERFACING
AN INTRODUCTION TO SERIAL PORT INTERFACING
 
Serial Communication Uart soc
Serial Communication  Uart socSerial Communication  Uart soc
Serial Communication Uart soc
 
INTERFACING WITH INTEL 8251A (USART)
INTERFACING WITH INTEL 8251A (USART)INTERFACING WITH INTEL 8251A (USART)
INTERFACING WITH INTEL 8251A (USART)
 
4 ql uart_psb_ds_revc
4 ql uart_psb_ds_revc4 ql uart_psb_ds_revc
4 ql uart_psb_ds_revc
 
Uart wiki
Uart wikiUart wiki
Uart wiki
 
Chapter5
Chapter5Chapter5
Chapter5
 

Recently uploaded

OOPS_Lab_Manual - programs using C++ programming language
OOPS_Lab_Manual - programs using C++ programming languageOOPS_Lab_Manual - programs using C++ programming language
OOPS_Lab_Manual - programs using C++ programming language
PreethaV16
 
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
upoux
 
Properties of Fluids, Fluid Statics, Pressure Measurement
Properties of Fluids, Fluid Statics, Pressure MeasurementProperties of Fluids, Fluid Statics, Pressure Measurement
Properties of Fluids, Fluid Statics, Pressure Measurement
Indrajeet sahu
 
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEERDELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
EMERSON EDUARDO RODRIGUES
 
Beckhoff Programmable Logic Control Overview Presentation
Beckhoff Programmable Logic Control Overview PresentationBeckhoff Programmable Logic Control Overview Presentation
Beckhoff Programmable Logic Control Overview Presentation
VanTuDuong1
 
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdfAsymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
felixwold
 
Impartiality as per ISO /IEC 17025:2017 Standard
Impartiality as per ISO /IEC 17025:2017 StandardImpartiality as per ISO /IEC 17025:2017 Standard
Impartiality as per ISO /IEC 17025:2017 Standard
MuhammadJazib15
 
Digital Twins Computer Networking Paper Presentation.pptx
Digital Twins Computer Networking Paper Presentation.pptxDigital Twins Computer Networking Paper Presentation.pptx
Digital Twins Computer Networking Paper Presentation.pptx
aryanpankaj78
 
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
Transcat
 
Accident detection system project report.pdf
Accident detection system project report.pdfAccident detection system project report.pdf
Accident detection system project report.pdf
Kamal Acharya
 
openshift technical overview - Flow of openshift containerisatoin
openshift technical overview - Flow of openshift containerisatoinopenshift technical overview - Flow of openshift containerisatoin
openshift technical overview - Flow of openshift containerisatoin
snaprevwdev
 
Introduction to Computer Networks & OSI MODEL.ppt
Introduction to Computer Networks & OSI MODEL.pptIntroduction to Computer Networks & OSI MODEL.ppt
Introduction to Computer Networks & OSI MODEL.ppt
Dwarkadas J Sanghvi College of Engineering
 
Determination of Equivalent Circuit parameters and performance characteristic...
Determination of Equivalent Circuit parameters and performance characteristic...Determination of Equivalent Circuit parameters and performance characteristic...
Determination of Equivalent Circuit parameters and performance characteristic...
pvpriya2
 
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
IJCNCJournal
 
Object Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOADObject Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOAD
PreethaV16
 
FULL STACK PROGRAMMING - Both Front End and Back End
FULL STACK PROGRAMMING - Both Front End and Back EndFULL STACK PROGRAMMING - Both Front End and Back End
FULL STACK PROGRAMMING - Both Front End and Back End
PreethaV16
 
Introduction to Artificial Intelligence.
Introduction to Artificial Intelligence.Introduction to Artificial Intelligence.
Introduction to Artificial Intelligence.
supriyaDicholkar1
 
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASICINTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
GOKULKANNANMMECLECTC
 
paper relate Chozhavendhan et al. 2020.pdf
paper relate Chozhavendhan et al. 2020.pdfpaper relate Chozhavendhan et al. 2020.pdf
paper relate Chozhavendhan et al. 2020.pdf
ShurooqTaib
 
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
DharmaBanothu
 

Recently uploaded (20)

OOPS_Lab_Manual - programs using C++ programming language
OOPS_Lab_Manual - programs using C++ programming languageOOPS_Lab_Manual - programs using C++ programming language
OOPS_Lab_Manual - programs using C++ programming language
 
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
一比一原版(uofo毕业证书)美国俄勒冈大学毕业证如何办理
 
Properties of Fluids, Fluid Statics, Pressure Measurement
Properties of Fluids, Fluid Statics, Pressure MeasurementProperties of Fluids, Fluid Statics, Pressure Measurement
Properties of Fluids, Fluid Statics, Pressure Measurement
 
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEERDELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
DELTA V MES EMERSON EDUARDO RODRIGUES ENGINEER
 
Beckhoff Programmable Logic Control Overview Presentation
Beckhoff Programmable Logic Control Overview PresentationBeckhoff Programmable Logic Control Overview Presentation
Beckhoff Programmable Logic Control Overview Presentation
 
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdfAsymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
Asymmetrical Repulsion Magnet Motor Ratio 6-7.pdf
 
Impartiality as per ISO /IEC 17025:2017 Standard
Impartiality as per ISO /IEC 17025:2017 StandardImpartiality as per ISO /IEC 17025:2017 Standard
Impartiality as per ISO /IEC 17025:2017 Standard
 
Digital Twins Computer Networking Paper Presentation.pptx
Digital Twins Computer Networking Paper Presentation.pptxDigital Twins Computer Networking Paper Presentation.pptx
Digital Twins Computer Networking Paper Presentation.pptx
 
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
Tools & Techniques for Commissioning and Maintaining PV Systems W-Animations ...
 
Accident detection system project report.pdf
Accident detection system project report.pdfAccident detection system project report.pdf
Accident detection system project report.pdf
 
openshift technical overview - Flow of openshift containerisatoin
openshift technical overview - Flow of openshift containerisatoinopenshift technical overview - Flow of openshift containerisatoin
openshift technical overview - Flow of openshift containerisatoin
 
Introduction to Computer Networks & OSI MODEL.ppt
Introduction to Computer Networks & OSI MODEL.pptIntroduction to Computer Networks & OSI MODEL.ppt
Introduction to Computer Networks & OSI MODEL.ppt
 
Determination of Equivalent Circuit parameters and performance characteristic...
Determination of Equivalent Circuit parameters and performance characteristic...Determination of Equivalent Circuit parameters and performance characteristic...
Determination of Equivalent Circuit parameters and performance characteristic...
 
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
Particle Swarm Optimization–Long Short-Term Memory based Channel Estimation w...
 
Object Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOADObject Oriented Analysis and Design - OOAD
Object Oriented Analysis and Design - OOAD
 
FULL STACK PROGRAMMING - Both Front End and Back End
FULL STACK PROGRAMMING - Both Front End and Back EndFULL STACK PROGRAMMING - Both Front End and Back End
FULL STACK PROGRAMMING - Both Front End and Back End
 
Introduction to Artificial Intelligence.
Introduction to Artificial Intelligence.Introduction to Artificial Intelligence.
Introduction to Artificial Intelligence.
 
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASICINTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
INTRODUCTION TO ARTIFICIAL INTELLIGENCE BASIC
 
paper relate Chozhavendhan et al. 2020.pdf
paper relate Chozhavendhan et al. 2020.pdfpaper relate Chozhavendhan et al. 2020.pdf
paper relate Chozhavendhan et al. 2020.pdf
 
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
A high-Speed Communication System is based on the Design of a Bi-NoC Router, ...
 

Universal Asynchronous Receive and transmit IP core

  • 1. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 2 Universal Asynchronous Receive and transmit IP core Aneesh Raveendran aneeshr2020@gmail.com ER&DCI Institute of Technology, Centre for Development of Advanced Computing(C-DAC), Thiruvananthapuram, Kerala CHAPTER 2
  • 2. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 3 INTRODUCTION The RS-232 serial communication protocol is a standard protocol used in asynchronous serial communication. It is a primary protocol used over modem line. It is used for connecting DTE (Data Terminal Equipment) and DCE (Data Circuit terminating Equipment).The protocol was standardised by EIA (Electronic Industry Association). The standard defines the electrical characteristics, timing of signals, the meaning of signals, the physical size and pin out of connectors. RS232 physical properties: The RS232 standard describes a communication method capable of communicating in different environments. This has had its impact on the maximum allowable voltages etc. on the pins. The maximum baud rate defined for example is 20 kbps. With current devices like the 16550A UART, maximum speeds of 1.5 Mbps are allowed. Voltages: The signal level of the RS232 pins can have two states. A high bit, or mark state is identified by a negative voltage and a low bit or space state uses a positive value. This might be a bit confusing, because in normal circumstances, high logical values are defined by high voltages also. The voltage limits are shown below. Level Transmitter capable (V) Receiver capable (V) Space state (0) +5 ... +15 +3 ... +25 Mark state (1) -5 ... -15 -3 ... -25 Undefined - -3 ... +3 Table 1: RS232 voltage values NOTE: Despite the high voltages present, it is not possible to destroy the serial port by short circuiting. Only applying external voltages with high currents may eventually burn out the driver chips. Still then, the UART won't be damaged in most cases. Maximum cable length:
  • 3. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 4 The maximum cable length is 50 feet, or the cable length equal to a capacitance of 2500 pF. This means that using a cable with low capacitance allows you to span longer distances without going beyond the limitations of the standard. If for example UTP CAT-5 cable is used with a typical capacitance of 17 pF/ft, the maximum allowed cable length is 147 feet. The cable length mentioned in the standard allows maximum communication speed to occur. If speed is reduced by a factor 2 or 4, the maximum length increases dramatically. Texas Instruments has done some practical experiments years ago at different baud rates to test the maximum allowed cable lengths. Keep in mind, that the RS232 standard was originally developed for 20 kbps. By halving the maximum communication speed, the allowed cable length increases a factor ten. Baud rate Maximum cable length (ft) 19200 50 9600 500 4800 1000 2400 3000 Table 2: RS232 cable length according to Texas Instruments
  • 4. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 5 FRAME FORMAT A frame is a complete and non-divisible packet of bits. A frame includes both information (e.g., data and characters) and overhead (e.g., start bit, error checking and stop bits). In asynchronous serial protocols such as RS-232, the frame consists of one start bit, seven or eight data bits, parity bits, and stop bits. A timing diagram for an RS-232 frame consisting of one start bit, 7 data bits, one parity bits and two stop bits is shown below in figure. Fig 2 : RS-232 Frame (1 start bit, 7 data bits, 1 parity bits, and 2 stop bits) The start bit is used to signal the beginning of a frame and the stop bit is used to signal the end of a frame. Parity is used to detect transmission errors. For even parity checking, the number of 1's in the data plus the parity bit must equal an even number. For odd parity, this sum must be an odd number. Parity bits are used to detect errors in transmitted data. Before sending out a frame, the transmitter sets the parity bit so that the frame has either even or odd parity. The receiver and transmitter have already agreed upon which type of parity check (even or odd) is being used. When the frame is received, then the receiver checks the parity of the received frame. If the parity is wrong, then the receiver knows an error occurred in transmission and the receiver can request that the transmitter re-send the frame.
  • 5. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 6 CHAPTER 3 SERIAL COMMUNICATION Serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. Figure shows the relationship between the various components in a serial link. These components are the UART, the serial channel, and the interface logic. An interface chip known as the universal asynchronous receiver/transmitter or UART is used to implement serial data transmission. The UART sits between the host computer and the serial channel. Fig 3: Asynchronous (RS-232) serial link The serial communication link mainly consisting of three components, UART LEVEL SHIFTER RS232 CONNECTOR
  • 6. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 7 CHAPTER 4 DESIGN SPECIFICATION Fig 4: Top level entity-IP core NAME DESCRIPTION CONNECTOR 9-PIN START BIT 1 DATA BIT 8 PARITY BIT NONE STOP BIT 1 BAUD RATE 1200,2400,4800,9600,19200,38400,57600, 115200 DEFAULT BAUD RATE 9600 Table 3: Design specification TXINT DATA_IN N BRR TDRE EN SCLK UART RXD TXD RXINT RDRF DATA_OUT RST
  • 7. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 8 CHAPTER 5 UART-Universal Asynchronous Receiver/Transmitter It is a type of "asynchronous receiver/transmitter". UART is a piece of hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signalling levels and methods (such as differential signalling etc.) typically are handled by a special driver circuit external to the UART. 8 1 TXD ENABLE SCLK BRR DA A 8 1 RXDDATA_OUT 8 8 Uart Transmitter Baud Rate Generator Uart Receiver Control Reg. DATA_IN 8
  • 8. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 9 Fig 5: General block diagram of UART CHAPTER 6 UART TRANSMITTER UART transmitter converts parallel data into serial data. It accepts 8-bit input data from the data bus or processor and converts it into serial data. The top level entity of UART transmitter is shown below 8 EN TDRE TXD TXINT Fig 6: Top level entity of UART Transmitter The UART transmitter accepts the 8-bit data through Data_in and performs the serializing action on the input data. The microprocessor can write the data into Data_in, only by checking the TDRE (Transmit Data Register Empty) pin. Logic 1 on TDRE represents the Transmit data register is empty and the transmission is possible, otherwise transmission is not possible. After the completion of the transmission the UART transmitter produces Transmission complete interrupt (TXINT).The UART transmitter is working on the clock produce by the Baud rate generator. The uart transmitter is only active when a high input signal is in the Enable pin. UART TRANSMITTER DATA_IN BCLK RST
  • 9. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 10 SERIALIZER BCLK TDRE TXD TXINT EN RST SCSR SERIALIZER Fig 7: Internal diagram-UART Transmitter SIGNAL EXPANSION LENGTH EN Enable 1 BCLK Baud Rate Clock 1 DATA_IN Input Data 8 RST System Reset 1 TDR (8) TSR (10) TRANSMIT CONTROL 6 5 4 3 2 1 0TDRE DATA_IN 8
  • 10. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 11 SCSR Serial Control Status Register 8 TDR Transmit Data Register 8 TDRE Transmit Data Register Empty 1 TSR Transmit Shift Register 10 TXD Transmit Data 1 TXINT Transmission complete Interrupt 1 Table 4: Signals in UART Transmitter SM CHART FOR UART TRAMSMITTER 0 -- state --operation 1 --condition 0 1 0 1 RESET bclk IDLE TDRE TDR Data_in set TDRE form TSR SYNCH bclk clear TSR(0) TXDATA EN=1
  • 11. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 12 0 1 CHAPTER 7 UART RECEIVER UART receiver converts serial data into parallel data. It performs the de-serializing action on the input data. The top level entity of UART receiver is shown below 8 EN RDRF RXINT RXD BCLK RST Fig 8: Top level entity-UART Receiver It accepts set of single bits from the input and converts it into a parallel (8-bit) data. The received data is given to the processor data bus. The processor can read the data from Receive Data Register (RDR), only the Receive Data Register is full (RDRF). Once the bclk Tcnt=9Set TXINT Clear Tcnt Reset TDRE TXD TSR(Tcnt) inc Tcnt UART RECEIVER DATA_OUT BCLKx8
  • 12. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 13 RSR (10) Receive Data register is full, the UART controller make the pin RDRF (Receive Data Register Full) high. Once the reception is completed the UART controller generates a Reception complete interrupt (RXINT). The bit stream coming from the RXD pin is not synchronized with the clock (bclk). If we attempt to read the RXD at the rising edge of bclk we would have a problem if RXD changed near the clock edge. And also we would have a setup and hold time problems. To ensure the start bit an oversampling procedure is used. The uart receiver is active only when a high input signal is applied to EN pin. RXD start bit 1st data bit 2nd data bit * * * BCLKx8 Fig 9: Oversampling DE-SERIALIZER EN RDRF RXD RXINT BCLK BCLKx8 RECEIVE CONTROL BCLK DATA_OUT 8 RSR (10)RDR (8)
  • 13. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 14 RST SCSR Fig 10: Internal diagram-UART Receiver SM CHART FOR UART RECEIVER 1 0 0 1 RDRF 5 4 3 2 1 07 RESET clk IDLE RXD START_DETECT clkx8 RXDClear cnt1 R EN=1
  • 14. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 15 1 0 1 0 (Contd…………..) 0 1 Cnt1=3 Inc cnt1Clear cnt1 X x RXDATA clkx8 Inc cnt1 cnt1=7 Cnt2=8 Shift RSR Inc cnt2 Clear cnt1 R
  • 15. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 16 0 1 0 1 CHAPTER 8 BAUD RATE GENERATOR In telecommunications and electronics, baud is synonymous to symbols per second or pulses per second. It is the unit of symbol rate, also known as baud rate or modulation rate; the number of distinct symbol changes (signalling events) made to the transmission medium per second in a digitally modulated signal or a line code. The baud rate is used for the communication purpose and it is used to identify that how much of the data had been transferred but at how much speed. The top level entity is shown below, BRR BCLK SCLK RST Fig 11: Top Level Entity- Baud Rate Generator 8 EN RDR RSR Generate TXINT Set RDRF Clr cnt1 Clr cnt2 clk INTERUPT BAUD RATE GENERATOR BCLKx8
  • 16. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 17 The baud rate generator generates the clock signal according to the baud rate Register (BRR). The below table shows the different baud rate register and the Baud rate that we used in our design. Baud Rate Register Baud Rate 00000011 1200 00000001 2400 00000010 4800 00000000 9600 00000100 19200 00000101 38400 00000110 57600 00000111 115200 Table 5: Baud Rate Register and Baud Rate CHAPTER 9 SIMULATION RESULTS Fig 12: UART Transmitter
  • 17. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 18 Fig 13: UART Receiver Fig 14: Baud Rate Generator CHAPTER 10 SYNTHESIS The UART IP core is synthesized using ALTERA QUARTUS II version 11.0 for ALTERA Stratix FPGA series number EP2S15F672C3. The total device utilization of uart IP core for above series is shown in Fig15.
  • 18. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 19 Fig15: Device Utilization of UART IP core Fig 16: Maximum Frequency of UART IP core Figure 16 shows the maximum frequency supported by the FPGA. The table 6 shows the summary of the device utilization of UART IP core. PARAMETER USAGE PERCENTAGE Logic Utilization 1% Combinational ALUTs 151/12480 1%
  • 19. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 20 Dedicated Logic Registers 87/12480 1% Total Registers 83 0% Total Pins 33/367 9% Total PLL and DLL 0 0% Max. Frequency 396.1MHz Table 6: Device Utilization -Summary The figure 17 shows the Register Transfer Level (RTL) view of the UART IP core. It consists of the RTL view of uart Transmitter, receiver and baud rate generator. Fig 17: RTL View –Top Level entity Figure 18 shows the hardware representation of baud rate generator, Fig 19 represents the hardware representation of uart Receiver, and Fig 20 represents the implementation of state diagram used for UART Receiver in ALTERA QUARTUS II.
  • 20. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 21 Fig 18: Hadware Representation-Baud Rate Generator Fig 19: : Hadware Representation-UART Receiver
  • 21. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 22 Fig 20: State Diagram in UART Receiver by ALTERA
  • 22. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 23 Fig 21: Hadware Representation-UART Transmitter CHAPTER 11 TESTING-UART The UART IP core is tested using ALTERA STRATIX FPGA series number EP2S15F672C3 and a Personal Computer. The synthesised netlist is downloaded into the FPGA and ready for testing. The testing structure of the IP core is divided into three phases. Phase 1: Transmitter testing The transmitter is tested by placing a random data in DATA_IN pin of the transmitter and a baud rate generator into the FPGA. After the successful implementation of Transmitter IP core in the FPGA, then connect the FPGA board into the personal computer. The steps for transmitter testing are listed below. 1) Place a random data in DATA_IN pin of the UART transmitter. 2) Fix the Baud Rate for transmission 3) Synthesis and download the netlist into the FPGA 4) Connect the FPGA board into the Personal Computer 5) Establish a connection between the FPGA board and Personal Computer using a Hyper Terminal 6) After the successful connection establishment Press RESET signal in FPGA 7) The stored data is printed in the Hyper Terminal; if this data is matched with stored data then UART transmitter is working correctly 8) Repeat the above steps for various data and baud rates Phase 2: Receiver testing The UART receiver is tested by sending an 8 bit of serial data through RXD pin. The receiver is tested by downloading uart receiver and a baud rate generator circuit. The steps used are listed below. 1) Fix the Baud Rate for transmission 2) Synthesis and download the netlist into the FPGA 3) Connect the FPGA board into the Personal Computer
  • 23. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 24 4) Establish a connection between the FPGA board and Personal Computer using a Hyper Terminal 5) send a character through Hyper Terminal using a key board 6) If the data is received successfully in the FPGA then a LED of FPGA will be glow 7) Repeat the above steps for various data and baud rates Phase 3: UART IP core testing The entire UART IP core is tested using a loop back structure. Figure 22 shows the UART testing structure. Fig 22: Loop Back Structure The steps used for UART IP core testing is shown is below. 1) Fix the Baud Rate for transmission 2) Synthesis and download the netlist into the FPGA 3) Connect the FPGA board into the Personal Computer 4) Establish a connection between the FPGA board and Personal Computer using a Hyper Terminal 5) send a character through Hyper Terminal using a key board 6) Checks the receiver section of the Hyper Terminal, if the received data is matched with the transmitted data, then the UART IP core is working properly. 7) Repeat the above steps with different baud rates. Fig 23 shows the test result of UART transmitter with character ‘ A’ at baud rate 115200Hz. Fig 24 shows the test result of UART transmitter with character ‘ AF’ at baud rate 1200Hz. Fig 25 shows the test result of entire UART IP core at baud rate 115200Hz.
  • 24. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 25 Fig23: Transmitting ‘A’ at 1115200 Hz
  • 25. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 26 Fig24: Transmitting ‘AF’ at 1200 Hz
  • 26. Universal Asynchronous Receive and Transmit IP core ER & DCI-IT, CDAC TVM Page 27 Fig 25: UART at 115200 Hz