Unit 1c
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This document discusses various topics related to embedded system design including: 1. It describes the CRC (Classes, Responsibilities, Collaborators) card methodology for turning a specification into an architecture design. An example of CRC cards for an elevator system is provided. 2. It discusses quality assurance and standards like ISO 9000 and the Capability Maturity Model for ensuring systems work properly. 3. It covers designing with computing platforms, including choosing hardware and software components, development environments, and debugging techniques like logic analyzers and breakpoints. 4. Consumer electronics architectures are discussed, including requirements for multimedia devices, use cases for playback and connectivity, and typical hardware components like CPUs and DSPs.
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This document discusses applications of operational amplifiers including peak detectors and instrumentation amplifiers. A peak detector uses an op-amp in a voltage follower configuration to either charge or discharge a capacitor based on the input voltage being greater than or less than the capacitor voltage. An instrumentation amplifier is used to measure small potential differences and provides benefits like high input impedance and common mode rejection. It operates by using three op-amps in a circuit to produce an output voltage proportional to the difference between its two inputs.
U3 op amp applications
This document discusses applications of operational amplifiers including instrumentation amplifiers, log and antilog amplifiers, active filters, comparators, waveform generators, clippers and clampers. Specifically, it covers log amplifiers using diodes or transistors with op-amps, temperature compensation circuits, and comparators which compare two inputs and output a signal. The document is a lecture on linear integrated circuits and their applications presented by an assistant professor.
Unit 1 ic fab
The document discusses the basic processes involved in the fabrication of monolithic integrated circuits. It describes the key steps which include silicon wafer preparation using the Czochralski crystal growth technique, epitaxial growth, oxidation, photolithography, diffusion, ion implantation, isolation techniques, metallization, and assembly/packaging. The overall goal is to introduce various impurities into a silicon wafer in precise locations and patterns to create the different components of an integrated circuit such as transistors, resistors and interconnects on a single silicon chip.
Fabrication of diodes, resistors, capacitors, fe ts
This document discusses the fabrication of different types of diodes and integrated circuits. It describes the fabrication process of Schottky barrier diodes using metal-semiconductor contacts and their low storage time characteristics. It also summarizes the fabrication of different types of integrated resistors like diffused, epitaxial, pinched, and thin film resistors. Additionally, it covers the construction of integrated junction and MOS capacitors. Finally, it outlines the fabrication process for JFET, MOSFET and CMOS devices.
Unit 3 part2
Program-level performance analysis.
Optimizing for:
Execution time.
Energy/power.
Program size.
Program validation and testing
Unit 3 part2
Program-level performance analysis.
Optimizing for:
Execution time.
Energy/power.
Program size.
Program validation and testing
Unit 3 part2
The document discusses various topics related to program design and analysis including:
1) Program-level performance analysis to understand execution time on complex platforms and optimize for time, energy, and size.
2) Measuring program performance using simulation, timers, or logic analyzers and analyzing metrics like average, worst, and best-case execution times.
3) Optimizing program performance by analyzing paths, loops, instruction timing considering factors like caches, pipelines, and data-dependent variations.
4) Validating program functionality through testing strategies like black-box and clear-box testing that examine inputs, outputs, and execution paths to verify correct behavior.
Compiler optimization
A compiler is a program that translates code written in one programming language into another language. Compilation has two phases - translation and optimization. The basic compilation phases are parsing, symbol table construction, machine-independent optimizations, machine-dependent optimizations, and assembly code generation. Compiler optimizations improve performance by techniques like dead code elimination, loop transformations, register allocation, instruction scheduling, and software pipelining.
Embedded programming u3 part 1
This document discusses embedded programming and is divided into several sections. It begins by stating the objectives and describing the target system. It then covers the main components of an embedded program including finite state machines, circular buffers, and queues. Different models of program design are explained such as C-text, data flow graphs, and control-data flow graphs. Finally, it discusses the processes of assembly, linking, and loading which involve generating symbol tables, combining object modules, and resolving addresses across modules in two phases.
ARM stacks, subroutines, Cortex M3, LPC 214X
The document summarizes the key features of the ARM Cortex-M3 microcontroller and the NXP LPC2148 microcontroller. Some key points:
- The ARM Cortex-M3 is a 32-bit microcontroller with a three-stage pipeline, optional memory protection unit, and low power modes. It has peripherals like timers, serial interfaces, and analog to digital converters.
- The LPC2148 is a 32-bit microcontroller based on the ARM7 architecture. It has features like 32kB RAM, 512kB flash, 10-bit ADC, USB, UART, I2C, SPI, timers and watchdog timer.
- Both microcontrollers support low power
ARM inst set part 2
1. The document discusses various ARM instruction set categories including data processing, arithmetic, immediate, move, logical, shift, compare, data transfer, and control flow instructions. It explains the instruction format and provides examples.
2. Data processing instructions include arithmetic operations like addition, subtraction, multiplication and logical operations. Data transfer instructions cover load, store with different addressing modes.
3. Control flow instructions involve unconditional and conditional branches. Subroutines are implemented using branch and link (BL) which saves the return address in the link register.
ARM instruction set
The ARM instruction set defines how the CPU is controlled by software through instructions. It includes various types of instructions like data processing, data transfer, and control flow instructions. ARM uses 32-bit instructions and is heavily based on registers. It has 37 registers total. The ARM architecture is load/store, meaning there is no direct memory access - only load and store instructions can access memory. Instructions can conditionally execute and often use three operands.
ARM instruction set
The document discusses the ARM instruction set. It begins by defining the instruction set and describing the three states of operation: compiler, assembly, and object code. It then describes various types of instructions like data processing, data transfer, and control flow instructions. The rest of the document provides details on ARM characteristics, registers, conditional execution, addressing modes, and examples of instructions for common operations.
ARM Versions, architecture
This document discusses embedded and real-time systems based on ARM architecture. It covers the three modes of operation in ARM: ARM instruction set, Thumb instruction set, and Jazelle-DBX/RCT for accelerating Java and supporting interpreted languages. It also summarizes the different ARM architecture versions from ARMv7 to ARMv8, describing their instruction sets and features. Finally, it provides overviews of ARM registers, memory organization, and other key concepts.
Unit 1a train
This document discusses the design of an embedded system to control model trains. It describes the requirements, including controlling the speed of up to 8 trains and sending error detection messages. It explains the working principle, with the user controlling trains via a console that sends signals over the tracks. The document also covers the DCC electrical and communication standards used to encode commands on the rails. It provides conceptual specifications, including classes for the console system and train system with functions like receiving and interpreting messages to control the train motor.
Unit2 arm
This document provides an introduction to embedded and real-time systems, focusing on the ARM processor, its architecture and peripherals. It discusses ARM architecture versions and instruction sets. It also covers the differences between Von Neumann and Harvard computer architectures. Real-time applications and the ARM dataflow operation are introduced. Specific topics covered include ARM-based products, ARM nomenclature, ARM features like its 32-bit architecture, load/store model and 3-stage pipeline. It also discusses ARM registers, modes of operation and the program status register.
Unit 1a train
This document discusses the design of an embedded system to control model trains. It begins by describing the model train setup and controller mechanism. It then covers the embedded system design process, presenting requirements and a requirements form for the model train controller. The document explains the DCC standard protocol for model train control, including electrical standards for transmitting signals and packet formats. It provides conceptual and physical object-oriented specifications for the console and train classes and components, including how the train motor speed is controlled.
unit 2- OP AMP APPLICATIONS
This document discusses various applications of operational amplifiers (op-amps) including: sign changers, phase lag/lead circuits, voltage-current converters, current-voltage converters, adders, subtractors, voltage followers, instrumentation amplifiers, diode applications like rectifiers and detectors, and clippers/clampers. It provides analysis and derivations of circuits using op-amps for transconductance amplification, summing, buffering inputs, and precision signal conditioning for applications like sensors and data acquisition.
VLSI DESIGN- MOS TRANSISTOR
This document provides an overview of CMOS VLSI design. It begins with an introduction to CMOS technology, including the basic structure and operation of NMOS and PMOS transistors. It then discusses DC characteristics such as different operating regions and I-V curves. The document covers fabrication processes like oxidation, photolithography, and etching. It also shows cross-sections and mask views for a sample CMOS inverter, highlighting steps like forming the n-well and adding contacts, polysilicon, diffusion and metal layers.
Power Dissipation
This document discusses power dissipation in circuits. It outlines that the objective is to discuss sources of power dissipation including static and dynamic power dissipation. Static power dissipation occurs even when a circuit is idle and includes leakage currents through transistors. Dynamic power dissipation is related to switching behavior and charging/discharging of capacitances.
More from Karthik Vivek (20)
Fabrication of diodes, resistors, capacitors, fe ts
Fabrication of diodes, resistors, capacitors, fe ts
Recently uploaded
A review on techniques and modelling methodologies used for checking electrom...
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
ACEP Magazine edition 4th launched on 05.06.2024
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
DfMAy 2024 - key insights and contributions
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Dynamic Programming
Backtracking
Techniques for Graphs
Branch and Bound
一比一原版(UMich毕业证)密歇根大学|安娜堡分校毕业证成绩单专业办理
UMich毕业证原版定制【微信：176555708】【密歇根大学|安娜堡分校毕业证成绩单-学位证】【微信：176555708】（留信学历认证永久存档查询）采用学校原版纸张、特殊工艺完全按照原版一比一制作（包括：隐形水印，阴影底纹，钢印LOGO烫金烫银，LOGO烫金烫银复合重叠，文字图案浮雕，激光镭射，紫外荧光，温感，复印防伪）行业标杆！精益求精，诚心合作，真诚制作！多年品质 ,按需精细制作，24小时接单,全套进口原装设备，十五年致力于帮助留学生解决难题，业务范围有加拿大、英国、澳洲、韩国、美国、新加坡，新西兰等学历材料，包您满意。
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三.真实教育部学历学位认证（教育部存档！教育部留服网站永久可查）
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如果您处于以下几种情况：
◇在校期间，因各种原因未能顺利毕业……拿不到官方毕业证【微信：176555708】
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◇需要报考公务员、购买免税车、落转户口
◇申请留学生创业基金
留信网认证的作用:
1:该专业认证可证明留学生真实身份
2:同时对留学生所学专业登记给予评定
3:国家专业人才认证中心颁发入库证书
4:这个认证书并且可以归档倒地方
5:凡事获得留信网入网的信息将会逐步更新到个人身份内，将在公安局网内查询个人身份证信息后，同步读取人才网入库信息
6:个人职称评审加20分
7:个人信誉贷款加10分→ 【关于价格问题（保证一手价格）
我们所定的价格是非常合理的，而且我们现在做得单子大多数都是代理和回头客户介绍的所以一般现在有新的单子 我给客户的都是第一手的代理价格，因为我想坦诚对待大家 不想跟大家在价格方面浪费时间
对于老客户或者被老客户介绍过来的朋友，我们都会适当给一些优惠。
8:在国家人才网主办的国家网络招聘大会中纳入资料，供国家高端企业选择人才
选择实体注册公司办理，更放心，更安全！我们的承诺：可来公司面谈，可签订合同，会陪同客户一起到教育部认证窗口递交认证材料，客户在教育部官方认证查询网站查询到认证通过结果后付款，不成功不收费！
学历顾问：微信：176555708
Modelagem de um CSTR com reação endotermica.pdf
Modelagem em função de transferencia. CSTR não-linear.
Heap Sort (SS).ppt FOR ENGINEERING GRADUATES, BCA, MCA, MTECH, BSC STUDENTS
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
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本公司拥有海外各大学样板无数，能完美还原。
1:1完美还原海外各大学毕业材料上的工艺：水印，阴影底纹，钢印LOGO烫金烫银，LOGO烫金烫银复合重叠。文字图案浮雕、激光镭射、紫外荧光、温感、复印防伪等防伪工艺。材料咨询办理、认证咨询办理请加学历顾问Q/微741003700
【主营项目】
一.毕业证【q微741003700】成绩单、使馆认证、教育部认证、雅思托福成绩单、学生卡等！
二.真实使馆公证(即留学回国人员证明,不成功不收费)
三.真实教育部学历学位认证（教育部存档！教育部留服网站永久可查）
四.办理各国各大学文凭(一对一专业服务,可全程监控跟踪进度)
如果您处于以下几种情况：
◇在校期间，因各种原因未能顺利毕业……拿不到官方毕业证【q/微741003700】
◇面对父母的压力，希望尽快拿到；
◇不清楚认证流程以及材料该如何准备；
◇回国时间很长，忘记办理；
◇回国马上就要找工作，办给用人单位看；
◇企事业单位必须要求办理的
◇需要报考公务员、购买免税车、落转户口
◇申请留学生创业基金
留信网认证的作用:
1:该专业认证可证明留学生真实身份
2:同时对留学生所学专业登记给予评定
3:国家专业人才认证中心颁发入库证书
4:这个认证书并且可以归档倒地方
5:凡事获得留信网入网的信息将会逐步更新到个人身份内，将在公安局网内查询个人身份证信息后，同步读取人才网入库信息
6:个人职称评审加20分
7:个人信誉贷款加10分
8:在国家人才网主办的国家网络招聘大会中纳入资料，供国家高端企业选择人才
New techniques for characterising damage in rock slopes.pdf
rock mass characterization and New techniques for characterising damage in rock slopes
Building Electrical System Design & Installation
Guide for Building Electrical System Design & Installation
Low power architecture of logic gates using adiabatic techniques
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
Advanced control scheme of doubly fed induction generator for wind turbine us...
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Recently uploaded (20)
A review on techniques and modelling methodologies used for checking electrom...
A review on techniques and modelling methodologies used for checking electrom...
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
Design and Analysis of Algorithms-DP,Backtracking,Graphs,B&B
basic-wireline-operations-course-mahmoud-f-radwan.pdf
basic-wireline-operations-course-mahmoud-f-radwan.pdf
Heap Sort (SS).ppt FOR ENGINEERING GRADUATES, BCA, MCA, MTECH, BSC STUDENTS
Heap Sort (SS).ppt FOR ENGINEERING GRADUATES, BCA, MCA, MTECH, BSC STUDENTS
New techniques for characterising damage in rock slopes.pdf
New techniques for characterising damage in rock slopes.pdf
Low power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniques
Advanced control scheme of doubly fed induction generator for wind turbine us...
Advanced control scheme of doubly fed induction generator for wind turbine us...
Generative AI leverages algorithms to create various forms of content
Generative AI leverages algorithms to create various forms of content
Unit 1c
- 2. RECAP • DESIGN METHODS (T2M, Q, Cost) • Design FLOWS (5) • Requirement Analysis (2) • SPECIFICATION (SDL)
- 3. System analysis and architecture design > The acronym CRC stands for the following three major items - Classes - Responsibilities - Collaborators > In this section we consider how to turn a specification into an architecture design. > Methodology- CRC card 3
- 5. EX: CRC cards for elevator - Classes - Responsibilities - Collaborators 5
- 6. Elevator crc class responsibilities collaborators Elevator car* Move up and down Car control, car sensor, car control sender Car state Reads current position of car car sensor
- 8. > The quality of a product or service can be judged by how well it satisfies its intended function. > ISO 9000 > If process is crucial, > Documentation , communication are important > CMM- Capability Maturity Model > Initial, repeatable, defined, manages, optimizing 8
- 11. How to create an initial working embedded system How to ensure that the system works properly. To describes the use of the PC as an embedded computing platform. 11
- 12. EXAMPLE PLATFORMS > Architectures and components: - software; - hardware. 12
- 13. HARDWARE: >CPU >BUS >Memory >I/O Devices CHOOSING A PLATFORM . SOFTWARE: >Run Time Components (OS) >Support Components (bug) 13
- 14. INTELLECTUAL PROPERTY > Architectures and components: - Software Libraries; - Hardware design. - Schematics - Net lists 14
- 15. DEVELOPMENT ENVIRONMENT HOST: Software development on a PC TARGET: Hardware on which code will run COMMUNICATION Host & Target connected by the USB HOST FUNCTIONS COMPLIER CROSS COMPILER TEST BENCH 15
- 16. DEBUGGING TECHNIQUES 16 DEBUGGING TECHNIQUES SOFTWARE DEBUGGING TOOLS HARDWARE DEBUGGING TOOLS LOGIC ANALYZERMP-ICEBREAK POINT TOOLSERIAL PORT TOOL
- 17. SOFTWARE DEBUGGING TOOLS 17 SERIAL PORT TOOL Debugging process from the INITIAL SATE of an embedded system BREAK POINT TOOL To specify an address where the Program execution is to break LED To Flash when error detected ADVANTAGE Implementing break points does not require any external devices 17
- 18. HARDWARE DEBUGGING TOOLS 18 MP-ICE Micro Processor In Circuit Emulator Hardware tool to debug software ICE special version of MP that internal Registers to be stopped after reading Expensive
- 20. 2 MODES OF OEPARTION 20 STATE MODE TIMING MODE
- 21. STATE MODE: Sampling the values Uses its own system clock Per clock cycle one signal is sampled Less memory Sequential oriented problems 21
- 22. TIMIMG MODE: Sampling the values Uses its internal clock Per clock cycle SEVERAL signal is sampled MORE memory GLITCH oriented problems 22
- 24. OPERATION Systems data signals are sampled Each sample is copied in vector memory All peripherals must run at high speed as several samples per system clock is performed. After sampling gets over, MP used to control the display by providing the data stored in memory 24
- 26. USE CASES AND REQUIREMENTS 2 REQUIREMENT FUNCTIONAL REQUIREMENT: MULTIMEDIA- MP3 AUDIO, MPEG VIDEO, JPEG Images DATA STORAGE & MANAGEMENT- Memory COMMUNICATION- USB interface Nonfunctional requirements -typical battery 26
- 27. Use case for playing multimedia. > Use case: 27
- 28. use case for connecting to a client > USB or Internet 28
- 29. Hardware architectures: > CPU > runs the operating system, > runs the user interface, > maintains the file system, 29 DSP performs signal processing
- 30. FILE SYSTEMS DOS file systems: DOS file allocation table (FAT) developed by Microsoft FAT can be implemented on flash storage Flash memory: > Flash memory is a type of semiconductor memory provides permanent storage 30
- 32. 32 Performance depends on all the elements of the system: CPU. Cache. Bus. Main memory. I/O device.
- 33. data from memory to the CPU > read from the memory; > transfer over the bus to the cache; and > transfer from the cache to the CPU 33
- 34. Bandwidth as performance > T: # bus cycles. W-Bus width > P: bus clock period. > Total time for transfer: > D: data transformation. > O1 + O2 = overhead O . 34 t = TP
- 35. Bus bandwidth > T-total time taken to transfer N data > D-data transformation > O-Overhead > N-N bytes of data transfer > W-Width of the Bus. 35 Tbasic(N) = (D+O)(N/W)
- 36. Bus burst transfer bandwidth > T-total time taken to transfer N data in burst mode, B- Burst bus transformation > D-data transformation > O-Overhead > N-N bytes of data transfer > W-Width of the Bus. 36 Tburst(N) = (BD+O)N/(BW)
- 37. Memory aspect ratios The height/width ratio of a memory . Best AR depends on Amount of memory required. 37
- 38. Thank you! 38