This document provides an overview of embedded system design. It discusses the characteristics of embedded systems and examples of embedded devices. It then covers key aspects of embedded system design including optimization of design metrics like cost, size and power. Processor technologies like general purpose, single purpose and application specific processors are described. The document also discusses integrated circuit technologies like full custom, semi-custom ASICs and programmable logic devices.

1. Embedded System
Design
MODULE – 1
1

2. Contents
■ Embedded Systems overview
■ Design Challenge – optimizing design metrics
■ Technologies
– Processor Technology
– IC Technology
– Design Technologies
2

3. Overview
■ Nearly any computing system other than a desktop
computer
■ Dedicated functionality
■ Embedded within electronic/mechanical devices
■ Billions of units produced yearly versus millions of
desktop units
3

4. Examples
4
Consumer
Electronics
• Cell Phones
• Digital Cameras
• Video Games
Home
Appliances
• Microwave Ovens
• Washing Machines
Office
Automation
• Printer
• Scanner
• Copier
Business
Equipment
• Card Readers
• ATM
Automobiles
• Antilock Brakes
• Fuel Injection

5. Characteristics
 Single Functional
Exceptions
- Updating a program
- Swapping of programs
 Tightly Constrained
- Cost, Power, Speed, Size
 Reactive and Real Time
5

6. An Embedded System Example
A Digital Camera
6
Microcontroller
CCD preprocessor Pixel coprocessor
A2D
D2A
JPEG codec
DMA controller
Memory controller ISA bus interface UART LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD
 Single Functional – Always digital camera
 Tightly constrained – Low cost, Low power, Small, Fast
 Reactive and real time – Only to small extent

7. Design Challenge –
Optimizing Design
Metrics Goal
– Construct an implementation with desired functionality
 Design Challenge
– Simultaneously optimizing design metrics
 Design Metric
– Measurable feature of a system’s implementation
7

8. Common Design Metrics
• Unit cost: the monetary cost of manufacturing each copy of the
system, excluding NRE cost
• NRE cost (Non-Recurring Engineering cost): The one-time
monetary cost of designing the system
• Size: the physical space required by the system
• Performance: the execution time or throughput of the system
• Power: the amount of power consumed by the system
• Flexibility: the ability to change the functionality of the system
without incurring heavy NRE cost
8

9. • Time-to-prototype: the time needed to build a working
version of the system
• Time-to-market: the time required to develop a system
to the point that it can be released and sold to customers
• Maintainability: the ability to modify the system after
its initial release
• Correctness, safety, many more
9

10. Optimizing Design Metrics
■ Compete with one another
■ Improving one may worsen others
■ Expertize with both software
and hardware is required
• Comfortable with variety of hardware and software
implementation
• Migration from one technology to another
• Best for a given application and constraints
10
SizePerformance
Power
NRE cost

11. Optimizing Design Metric
(cont..)
11
Microcontroller
CCD preprocessor Pixel coprocessor
A2D
D2A
JPEG codec
DMA controller
Memory controller ISA bus interface UART LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD
Hardware
Software

12. Time to Market
 Time for development of a
product to the point it can be sold
to customers
 Market Window
Period where sales is highest
 Average time to market=8 months
 Delays are costly
12
Revenues($)
Time (months)
Market Window

13. Losses due to delayed market entry
13
On-time Delayed
entry entry
Peak revenue
Peak revenue from
delayed entry
Market rise Market fall
W 2W
Time 
D
On-time
Delayed
Revenues($)
■ Simplified revenue model
– Product life = 2W, peak at W
– Time to market entry defines a
triangle, representing market
penetration
– Triangle area equals revenue
■ Loss
– The difference between the on-
time and delayed triangle areas

14. Losses due to delayed market
entry
(cont…)
14
On-time Delayed
entry entry
Peak revenue
Peak revenue from
delayed entry
Market rise Market fall
W 2W
Time 
D
On-time
Delayed
Revenues($)
■ Area = 1/2 * base * height
– On-time = 1/2 * 2W * W
– Delayed = 1/2 * (W-D+W)*(W-D)
■ Percentage revenue loss =
(D(3W-D)/2W2)*100%
■ Examples
– Lifetime 2W=52 weeks, delay
D=4weeks  22%
– Lifetime 2W=52 weeks, delay
D=10weeks  50%
– Delays are costly!

15. Difficulty of meeting Time to
Market
15
• Increasing IC capacities
• Moore’s Law – Transistor density of chips doubles roughly every 18-24
months

16. NRE and Unit Cost Metrics
■ Costs:
– Unit cost: the monetary cost of manufacturing each copy of the
system, excluding NRE cost
– NRE cost (Non-Recurring Engineering cost): The one-time monetary
cost of designing the system
– Total cost = NRE cost + unit cost * # of units
– Per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
16
• Example
– NRE=$2000, unit=$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300

17. 17
$0
$40,000
$80,000
$120,000
$160,000
$200,000
0 800 1600 2400
A
B
C
$0
$40
$80
$120
$160
$200
0 800 1600 2400
Number of units (volume)
A
B
C
Number of units (volume)
totalcost(x1000)
perproductcost
■ Compare technologies by costs -- best depends on
quantity we produce
– Technology A: NRE=$2,000, unit=$100
– Technology B: NRE=$30,000, unit=$30
– Technology C: NRE=$100,000, unit=$2
• But, must also consider time-to-market
NRE and Unit Cost Metrics
(cont..)

18. Embedded System
Technologies■ Technology
– A manner of accomplishing a task, especially using
technical processes, methods, or knowledge
■ Three key technologies for embedded systems
– Processor technology
– IC technology
– Design technology
18

19. Processor Technology
■ The architecture of the computation engine used to implement
a system’s desired functionality
■ “Processors” programmable or non-programmable
■ It can be
– General-Purpose
– Application Specific
– Single-Purpose
19

20. Processor Technology (cont..)
20
total = 0
for i = 1 to N loop
total += M[i]
end loop
General-
purpose
processor
Single-
purpose
processor
Application-specific
processor
Desired
functionality
■ Processors vary in their customization for the problem at hand

21. General Purpose Processors
■ Programmable device used in a variety of
applications
■ Features
– Program memory
– General datapath with large register file and
general ALU
■ User benefits
– Low time-to-market and NRE costs
– High flexibility
– Unit cost relatively low in small quantities
■ Drawbacks
– Size and power consumption large
– Unit cost too high for large quantities
■ “Pentium”- Well known processor
21
IR PC
Register
file
General
ALU
DatapathController
Program
memory
Assembly
code for:
total = 0
for i =1 to …
Control
logic and
State
register
Data
memory

22. Single Purpose Processors
■ Digital circuit designed to execute
exactly one program
■ Features
– Contains only the components needed to
execute a single program
– No program memory
■ Benefits
– Fast
– Small size
– Low power
– Unit cost low for large quantities
■ Drawbacks
– Design time and NRE cost high
– Flexibility is low
– Unit cost high for small quantities eg ccd
22
DatapathController
Control
logic
State
register
Data
memory
index
total
+

23. Application Specific Processors
■ Designed for particular class of applications
– DSP, Telecommunication, Embedded Control
■ Compromise between general purpose and
single purpose
■ Features
– Program memory
– Optimized datapath
– Special functional units
■ Benefits
– Some flexibility
– Good performance, size and power
23
IR PC
Registers
Custom
ALU
DatapathController
Program
memory
Assembly
code for:
total = 0
for i =1 to …
Control
logic and
State
register
Data
memory

24. Application Specific Processors (ASIP)
■ Drawbacks
– Requires large NRE cost- to build processor and build
compiler
■ Researchers focus on making Retargetable Compilers
– Easy to modify to generate code for different
instruction set architectures
– Assembly language programming time consuming
■ But retargetable compilers are not easy to get  ASIP
write in assembly language time consumed more
24

25. Digital Signal Processors
■ Common class of ASIP’s
■ Common operations – Digital encodings of
analog signals like video and audio
– Operations- Filtering, Transformations or
combination
– Math operations- Multiply and add, Shift and add
■ Special purpose datapath units – Multiply accumulate
unit
25

26. IC Technology
■ Mapping of digital (gate level) implementation onto an
IC(Chip)
■ CMOS Technology is most commonly used
– High noise immunity
– Low static power consumption
– Large Fan Out
– Fast in operation
26

27. 27
• Semiconductor fabrication consists of different layers
 Bottom layer – Transistors
 Middle layer – Logic Gates
 Top layer – Connect the gates with wires
• Three categories
1. Full Custom/VLSI
2. Semi-Custom ASIC
3. Programmable Logic Devices (PLD)

28. Full-Custom/VLSI
■ Layout for each individual transistor is specified
■ Also interconnections between them
■ Optimization for
– Placing transistors to minimize interconnection lengths
– Sizing the transistors to optimize signal transmission
– Routing wires among transistors
28

29. 29
• Drawbacks
 High NRE cost
 Time consuming
• Used only for high volume or extremely performance
critical applications

30. Semi-custom ASIC
■ Partial amount of flexibility
■ Lower layers – fully or partially built
Upper layers – Left to the designer to finish
■ Designer can specify the position of gates in a layout
■ ASICS – Most popular IC technology
■ Provides good performance
■ Less NRE cost than Full custom IC’s
30

31. 31
Gates are taken from
• Gate array Technology
 A gate array is a prefabricated silicon chip with most
transistors having no predetermined function.
 These transistors can be connected by metal layers to form
standard NAND or NOR logic gates.
 These logic gates can then be further interconnected into a
complete circuit on the same or later metal layers.
 Creation of a circuit with a specified function is
accomplished by adding these final layer or layers of metal
interconnects to the chips late in the manufacturing
process, allowing the function of the chip to be customized
as desired.

32. 32
• Standard cell Technology
 Logic level cells (AND gate & AND-OR-INVERT) have their
masks pre-designed by hand
 Task - Arrange the portions into complete masks for gate
level and convert to cells.

33. Programmable Logic Devices
(PLD)■ All layers already exist
■ Layers implement a programmable circuit
– Programming consists of creating or destroying connections
between wires that connect gates
– By blowing a fuse or setting a bit in a programmable switch
■ Programmers connected to desktop computer can
perform such programming
33

34. Simple PLD
■ Programmable Logic Array (PLA)
– Programmable array of AND gates +
Programmable array of OR gates
34

35. ■ Programmable Array Logic (PAL)
– Programmable array of AND gates +
Fixed logic OR gates
– Only one is programmable  Reduces the
number of programmable components
35

36. Field Programmable Gate Arrays (FPGA)
■ Complex PLD
■ Offers more general connectivity
between blocks of logic
■ Used for complex designs
36

37. 37
• Advantages
 Less NRE cost
 Time required is less
• Drawbacks
 Bigger than ASIC’s
 May have higher unit costs
 May consume more power

38. Independence of Processor and IC
Technologies
38

39. Trends in IC Technology
■ Most important trend in embedded systems  trend related
to IC’s
■ Moore’s Law - Predicted in 1965 by Intel co-founder Gordon Moore
IC transistor capacity has doubled roughly every 18-24 months
for the past several decades
39
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic transistors per
chip
(in millions)

40. Graphical illustration of Moore’s law
40
1981 1984 1987 1990 1993 1996 1999 2002
Leading edge
chip in 1981
10,000
transistors
Leading edge
chip in 2002
150,000,000
transistors

41. Design Technology
■ The manner in which we convert our concept of
desired system functionality into an implementation
■ Top down Design Process
– Breaking down of a system to gain insight into its
compositional sub-systems.
41To final implementation

42. ■ System Level
– Desired functionality described in some language (English
or executable language like C)
■ Behavioral
– Specification refined by distributing portions of it among
several general and/or single purpose processor
■ Register-Transfer Level
– Converts behaviour on general purpose processors into
assembly code
– Behaviour on single purpose processor into a connection of
register transfer components and state machines
42

43. ■ Logic Level
– RT level specifications of single purpose processor into
logic level specifications of Boolean eqns.
– No refinement for general purpose processor’s assembly
code at this level
■ Designer refines the remaining specifications into an
implementation
– Machine code for general purpose processor
– Gate-level netlist for single purpose processor
43

44. Productivity Improvers
■ Compilation/Synthesis
■ Libraries/IP
■ Test/Verification
■ Each approach can be applied at any of the 4
abstraction levels.
44

45. Compilation/Synthesis
■ Allows a designer to specify desired functionality in an abstract
manner & automatically generate lower level implementation
details
■ System Synthesis Tool
– Converts an abstract system specification into a set of
sequential programs in general and single purpose
processors
■ Behavioral Synthesis Tool
– Converts sequential program into FSM’s and register
transfers
45

46. Compilation/Synthesis (cont..)
■ RT Synthesis Tool
– Converts FSM’s and register transfers into datapath of RT
components and a controller of Boolean equations
■ Logic Synthesis Tool
– Converts Boolean expressions into a connection of logic
gates NETLIST
46

47. Libraries/IP
■ Libraries Reuse of pre-existing implementations
■ Can improve productivity if the time it takes to find,
acquire, integrate and test a library item is less than
designing the item.
■ Logic level library
– Consists of layouts for gates and cells
■ RT level library
– Consists of layouts of RT components (registers, MUX,
decoders etc)
47

48. Libraries/IP (cont..)
■ Behavioral level library
– Commonly used components like compression components, bus
interfaces, display controllers etc
– The components should be capable of implementing one
portion of an IC CORES
– Change from behavioural level library of IC’s to libraries of cores
– ‘Intellectual Property (IP)’– cores exist in intellectual form that
must be protected from copying
■ System level library
– Complete system solving particular problems
– Interconnection of processors with OS and programs to
implement interface to internet
48

49. Test/Verification
■ Ensuring that the functionality is correct
■ Prevents time consuming debugging at low levels and
iterating back to higher levels
■ SIMULATION method for testing correct functionality
■ Logic Level
– Gate level simulators
– Output signal timing waveforms given input signal
waveforms
■ RT Level
– HDL simulators execute RT level descriptions and provide
output waveforms
49

50. Test/Verification (cont..)
■ Behavioral Level
– HDL simulators simulate sequential programs
– Co-simulators connect HDL and general purpose processor
simulators to enable hardware/software co-verification
■ System Level
– Model Simulator simulates initial system specification
– To verify correctness and completeness of system
– Also ensures that simultaneous conditions never occur or
system does not deadlock
50

51. Ideal Top Down Design Process
51

52. The co-design ladder
■ In the past:
– Hardware and
software design
technologies were
very different
■ Recent maturation of
synthesis enables a unified
view of hardware and
software
■ Hardware/software
“codesign”
52
The choice of hardware versus software for a particular function is simply
a tradeoff among various design metrics, like performance, power, size,
NRE cost, and especially flexibility; there is no fundamental difference
between what hardware or software can implement.

53. Design productivity gap
53
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic transistors
per chip
(in millions)
100,000
10,000
1000
100
10
1
0.1
0.01
Productivity
Transistors/
Designer-Month(K
IC capacity
productivity
Gap
• While designer productivity has grown at an impressive rate over the past
decades, the rate of improvement has not kept pace with chip capacity

54. Design productivity gap
■ 1981 leading edge chip required 100 designer months
– 10,000 transistors / 100 transistors/month
■ 2002 leading edge chip requires 30,000 designer
months
– 150,000,000 / 5000 transistors/month
■ Designer cost increase from $1M to $300M
54

55. Summary
■ Embedded systems are everywhere
■ Key challenge: optimization of design metrics
– Design metrics compete with one another
■ A unified view of hardware and software is necessary to
improve productivity
■ Three key technologies
– Processor: general-purpose, application-specific, single-purpose
– IC: Full-custom, semi-custom, PLD
– Design: Compilation/synthesis, libraries/IP, test/verification
55