The ARM instruction set defines how the CPU is controlled by software through instructions. It includes various types of instructions like data processing, data transfer, and control flow instructions. ARM uses 32-bit instructions and is heavily based on registers. It has 37 registers total. The ARM architecture is load/store, meaning there is no direct memory access - only load and store instructions can access memory. Instructions can conditionally execute and often use three operands.

1. ARM
INSTRUCTION
SET mr.C.KARTHIKEYAN
AP/ECE/RMKCET

2. Instruction SET
Defines how the hardware (CPU) is controlled by the software and understands the
language written by the user.
3 States of operation
2
compiler
HLL assembly
assembler
HLLHLL assemblyassembly
Object CodeObject Code

3. VARIOUS TYPES OF InstructionS
⩥ Data Processing
⩥ Data Transfer (REG- ANOTHER REG, REG- MY, MY-REG)
⩥ Control Flow (alters the sequence of instruction flow)
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4. ARM CHARACTERISTICS
37 Registers, 32 bit length
Heavily based on REGISTERS
Flexibility in the operation (2nd OP)
Faster response & HP with LP
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5. 5
The ARM Architecture is a Load/Store architecture
No direct manipulation of memory contents
Register files contains in all 37 registers
20 registers are hidden from program at different times
These registers are called banked registers (IRQ, FIQ, UNDEF, ABORT, SVC)
Banked registers are available only when the processor is in a particular mode
3-address data processing instructions
Conditional execution of every instruction {condition} {Rd}, Operand1, Operand2
Load and store multiple registers
Shift, ALU operation in a single instruction
Open instruction set extension through the co-processor instruction

6. 6
MNEMONIC - Short name (mnemonic) of the instruction
{S}
{condition} {Size} {Rd}, Operand1, Operand2
{S} - An optional suffix. If S is specified, the condition flags are updated on the result of the
operation
{condition}- Condition that is needed to be met in order for the instruction to be executed
{size}- byte ,half word, word
{Rd}- Register (destination) for storing the result of the instruction
Operand1 - First operand. Either a register or an immediate value
Operand2- Second (flexible) operand. Can be an immediate value (number) or a register with
an optional shift

7. 7
EQ Equals zero Z=1
NE Not equal to zero Z=0
CS Carry set C=1
CC Carry clear C=0
MI Minus N=1
PL Nonnegative (plus) N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 and Z=0
LS Unsigned lower or same C=0 or Z=1
GE Signed greater than or equal N=V
LT Signed less than N=V
GT Signed greater than Z=0 and N=V
LE Signed less than or equal Z=1 or N=V

8. endians
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9. Data Processing Instructions
.
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Basic format:
ADD r0,r1,r2
Computes r1+r2, stores in r0.
Immediate operand:
ADD r0,r1,#2
Computes r1+2, stores in r0.

10. LOGICAL Instructions
⩥ AND r0,r1,r2 ; r0=r1 & r2
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R2 0 0 1 1 0 0 1 1
R1 1 1 1 0 0 1 0 0
R0 0 0 1 0 0 0 0 0
ORR r0,r1,r2 ; r0=r1 + r2
EOR r0,r1,r2 ; r0=r1 r2
BIC r0,r1,r2 ; r0= r1 and not r2
R2 0 0 1 1 0 0 1 1
R1 1 1 1 0 0 1 0 0
R2` 1 1 0 0 1 1 0 0
R0 1 1 0 0 0 1 0 0

11. Moveinstruction
2 REG (1 S, 1D)
⩥ MOV r0, r2 ;
⩥ MOVN r0, r2 ; r0=not r2
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12. SHIFT Instructions (BARREL SHIFTER)
⩥ Logical shift:
⊳ fills with zeroes.
⩥ Arithmetic shift:
⊳ fills with ones.
⩥ RRX performs 33-bit rotate, including C
bit from CPSR above sign bit.
⩥ ADD r1,r2,r3, LSL #3 ; r1=r2+(r3<<3)
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13. COMPARE Instructions
⩥ When ALU solves as per the inst , the
flag reg always keep track , whether the
result is NZCV .
⩥ JUST COMPARE, ENABLE THE FLAG REG
FOR FUTURE USE
⩥ CMN r1,r2
⩥ TST r1,r2
⩥ TEQ r1,r2 ; r1 r2
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14. LOAD/STORE Instructions
⩥ Use to move data between one or two registers and
memory
LDRD STRD Doubleword
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
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15. Example 1: C assignment
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⩥ C: y = a*(b+c);
⩥ Assembler:
ADR r4,b ; get address for b
LDR r0,[r4] ; get value of b
ADR r4,c ; get address for c
LDR r1,[r4] ; get value of c
ADD r2,r0,r1 ; compute partial
result
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
MUL r2,r2,r0 ; compute final
value for y

16. Example 2: C assignment
⩥ C:x = (a + b) - c;
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17. ⩥ Assembler:
ADR r4,a ; get address
for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address
for b, reusing r4
LDR r1,[r4] ; get value of b
ADD r3,r0,r1 ; compute a+b
ADR r4,c ; get
address for c
LDR r2,[r4] ; get value of c
SUB r3,r3,r2 ; 17

18. Example 3: C assignment
⩥ C: z = (a << 2) | (b & 15);
⩥ Assembler:
ADR r4,a ; get
address for a
LDR r0,[r4] ; get
value of a
MOV r0,r0,LSL 2 ; perform shift
ADR r4,b ; get
address for b
LDR r1,[r4] ; get
value of b
AND r1,r1,#15 ; perform AND
ORR r1,r0,r1 ; perform OR 18

19. Additional addressing modes
⩥ Base-plus-offset addressing:
LDR r0,[r1,#16]
⊳ Loads from location r1+16
⩥ Auto-indexing increments base register:
LDR r0,[r1,#16]!
⩥ Post-indexing fetches, then does offset:
LDR r0,[r1],#16
⊳ Loads r0 from r1, then adds 16 to r1.
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20. Thanks!