1) Sequential circuits consist of combinational logic and memory elements like latches and flip-flops. 2) Memory elements can store digital values and change their values based on input signals like clock signals. Common memory elements include latches, D flip-flops, JK flip-flops, and T flip-flops. 3) Sequential circuits are important building blocks of CPUs as they allow for the storage and processing of digital signals over time.

1. Sequential Logic
Circuit
Yong Heui Cho @ Mokwon University
Most of slides are referred to and all credits should go to:
[1] M.Y. Idris & N.M. Noor, Sequential Circuit, slideshare.

2. Basic Computer Design
3. Basic Computer Architecture
4. Combinational Logic Circuit
5. Sequential Logic Circuit
6. CPU Architecture - Basic

3. Sequential Logic
• Sequential circuit consists of feedback path
and several memory elements
• Sequential circuit = Combinational Logic +
Memory Elements
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

4. Sequential Logic & CPU
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simplified CPU model

5. Memory Element
• Memory element device that can remember a
value for a certain period, or change value
based on the input instruction
• Example: Latch and flip-flop
Commands for latches include set and reset
commands
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

6. Latch & Flip-flop
• Latch: basic memory element to store 1 bit
• Flip-flop: commonly clocked latch
latch flip-flop SR flip-flop
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7. Flip-flop
• Flip-flop is a memory element which change its
condition based on clock signal
• Clock is a square waveform
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

8. SR Latch
• Basic SR latch
• Criteria table:
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)()1( tQRStQ 
□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

9. SR Latch Circuit
• NAND or NOR circuits
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74LS279

10. Gated SR Flip-flop
• SR latch, enable (EN) input, and 2 NAND gates
• Clear and preset
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11. D Flip-flop
• D = delay or data
• Make input R the same as S’ = D latch with gate
• D flip-flop eliminates invalid condition of SR latch.
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

12. Edge Triggered Flip-flop
• Edge triggered flip-flops are marked with “>”
symbol at clock input.
Positive edge triggered flip-flop
Negative edge triggered flip-flop
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

13. Gated D Flip-flop
• When EN is HIGH
– D=HIGH – latch is in SET
– D=LOW – latch is in RESET
• Therefore, when EN is HIGH, Q will follow input D
• Criteria table for positive edge trigger:
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DtQ  )1(
□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

14. Parallel Data Transaction
• Usage: to transfer 4-bit data inputs to outputs
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15. JK Flip-flop
• JK flip-flop
• Criteria table:
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)()()1( tQKtQJtQ 

16. T Flip-flop
• T = Toggle
• T flip-flop single input version for JK flip-flop,
formed by combining JK input
• Criteria table:
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)()()1( tQTtQTtQ 
□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.

17. Frequency Divider
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D flip-flop
T flip-flop

18. Master Slave Flip-flop
• Master is activated when positive edge and
Slave is activated when clock negative edge
triggered.
• Master Slave Flip-flop
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□ Courtesy to M.Y. IDRIS & N.M. NOOR, Sequential Circuit, slideshare.