This document provides an introduction to sequential circuits and various types of flip-flops. It discusses the differences between combinational and sequential circuits, and describes SR, D, JK, T, and JK flip-flops. Their block diagrams, truth tables, characteristic tables, and excitation tables are presented. Applications of flip-flops such as counters, frequency dividers, shift registers, and data storage are also covered briefly. Finally, the document discusses various types of shift registers including serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out.

1. MODULE -5
SEQUENTIAL CIRCUITS

2. Introduction to Sequential Circuits
 In sequential circuits, the present output depends on the present
input as well as previous output/output’s.
 Sequential circuits are very basic required concept for Flip-flop,
Counters and Registers.
Combinational
Circuits
IN OUT
MEMORY
Feedback

3. Difference Between Combinational Circuit
and Sequential Circuit
Combinational Circuit Sequential Circuit
The output depends on input only The output depends on present
inputs and past outputs
Memory elements are not required Memory elements are required to
store the past outputs.
This circuits are easy to design since
it contains only gates.
Sequential circuits are harder to
design
Combinational circuits are faster in
speed
Sequential circuits are slower than
combinational circuit
Example : Parallel Adder, Half
adder
Example: Counter, Register, Flip
Flop

4. Flip-Flops
 It is a sequential circuit which has two states( 0 and
1) and it can be used to store state information.
 Types of Flip-Flop
1. SR –Flip-Flop (Set and Reset)
2. D- Flip-Flop (Delay)
3. JK- Flip-Flop (Jack Kilby)
4. T- Flip-Flop(Toggel)

5. SR Flip-Flops
 It is a SR latch using NAND gates with an additional
enable input.
 Block Diagram

6. SR Flip-Flops
Circuit Diagram

7. SR Flip-Flops
Truth Table
CLK S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invalid

8. SR Flip-Flops
Characteritic Table
CLK S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invalid
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X

9. SR Flip-Flops
Excitation Table
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

10. D Flip-Flops
 It is also known as a "data" or "delay" flip-flop. The D flip-
flop captures the value of the D-input at a definite portion of the clock
cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output
Q does not change.
CLK S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Invalid

11. D Flip-Flops
Block Diagram
Truth Table
CLK D Qn+1
0 X Qn
1 0 0
1 1 1

12. D Flip-Flops
Characteristic Table
CLK D Qn+1
0 X Qn
1 0 0
1 1 1
Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1

13. D Flip-Flops
Excitation Table
Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

14. JK Flip-Flops
The J-K flip-flop is the most versatile of the basic flip-flops.
It has the input- following character of the clocked D flip-flop but has
two inputs, traditionally labeled J and K.
If J and K are different then the output Q takes the value of J at the next
clock edge.
Block Diagram

15. JK Flip-Flops
Circuit Diagram

16. JK Flip-Flops
Truth Table
Reference Table
CLK S R Qn+1
0 X X Qn
(Memory)
1 0 0 Qn
(Memory)
1 0 1 0
1 1 0 1
1 1 1 Invalid
CLK J K Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 ͞Qn

17. JK Flip-Flops
Characteristic Table
CLK J K Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 ͞Qn
(Toggle)
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

18. JK Flip-Flops
Excitation Table
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

19. T Flip-Flops
T flip – flop is an edge triggered device i.e. the low to high or high to
low transitions on a clock signal of narrow triggers that is provided as
input will cause the change in output state of flip – flop.
Block Diagram

20. T Flip-Flops
Circuit Diagram

21. T Flip-Flops
Truth Table
CLK T Qn+1
0 X Qn (Memory)
1 0 Qn (Memory)
1 1 ͞͞Qn (Toggling)

22. T Flip-Flops
Characteristic Table
CLK T Qn+1
0 X Qn (Memory)
1 0 Qn (Memory)
1 1 ͞͞Qn (Toggling)
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

23. T Flip-Flops
Excitation Table
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

24. LATCH
It is sequential circuit that checks all of its input continuously
and changes its output at anytime.
Latch is a sequential circuit which has two states( 0 and 1) and it
can be used to store state information.
Both Latch and Flip Flop are memory elements/ Storage
element.
Latch is used to design Asynchronous sequential circuit.
Flip Flop is used to design Synchronous sequential circuit.

25. LATCH
Asynchronous sequential circuits do not use clock
signals as synchronous circuits do
Types of Latch
1. SR –Latch (Set and Reset)
2. D- Latch (Delay)
3. JK- Latch (Jack Kilby)
4. T- Latch (Toggel)

26. CS1104-11
Memory Elements
26
Memory Elements
 Memory element with clock. Flip-flops are memory
elements that change state on clock signals.
 Clock is usually a square wave.
command
Memory
element stored value
Q
clock
Positive edges Negative edges
Positive pulses

27. CS1104-11
Memory Elements
27
Memory Elements
 Two types of triggering/activation:
 pulse-triggered
 edge-triggered
 Pulse-triggered
 latches
 ON = 1, OFF = 0
 Edge-triggered
 flip-flops
 positive edge-triggered (ON = from 0 to 1; OFF = other
time)
 negative edge-triggered (ON = from 1 to 0; OFF = other
time)

28. CS1104-11
S-R Latch
28
S-R Latch
 Complementary outputs: Q and Q'.
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET state.
 For active-HIGH input S-R latch (also known as
NOR gate latch),
R=HIGH (and S=LOW) a RESET state
S=HIGH (and R=LOW) a SET state
both inputs LOW a no change
both inputs HIGH a Q and Q' both LOW (invalid)!

29. CS1104-11
S-R Latch
29
S-R Latch
 Characteristics table for active-high input S-R
latch:
S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
S
R
Q
Q'

30. CS1104-11
S-R Latch
30
S-R Latch
 Active-HIGH input S-R latch
R
S
Q
Q'
S R Q Q'
1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
0 0 0 1 (after S=0, R=1)
1 1 0 0 invalid!
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0

31. CS1104-11
Gated D Latch
31
Gated D Latch
 Make R input equal to S'  gated D latch.
 D latch eliminates the undesirable condition of
invalid state in the S-R latch.
D
EN
Q
Q'
D
Q
Q'
EN

32. CS1104-11
Gated D Latch
32
Gated D Latch
 When EN is HIGH,
 D=HIGH  latch is SET
 D=LOW  latch is RESET
 Hence when EN is HIGH, Q ‘follows’ the D
(data) input.
 Characteristic table:
When EN=1, Q(t+1) = D
EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

33. CS1104-11
Gated D Latch
33
Latch Circuits: Not Suitable
 Latch circuits are not suitable in synchronous
logic circuits.
 When the enable signal is active, the excitation
inputs are gated directly to the output Q. Thus,
any change in the excitation input immediately
causes a change in the latch output.
 The problem is solved by using a special timing
control signal called a clock to restrict the times
at which the states of the memory elements
may change.
 This leads us to the edge-triggered memory
elements called flip-flops.

34. Steps To Convert from One FlipFlop to
Other :
1. Let there be required flipflop to be constructed
using sub-flipflop:
2. Draw the truth table of required flipflop.
3. Write the corresponding outputs of sub-flipflop
to be used from the excitation table.
4. Draw K-Maps using required flipflop inputs and
obtain excitation functions for sub-flipflop
inputs.
5. Construct logic diagram according to the
functions obtained.
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35. Conversion for FlipFlops
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EXCITATION TABLE:

36. i) Convert SR To JK FlipFlop
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37. Excitation Functions:
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38. ii Convert SR To D FlipFlop:
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39. Excitation Functions:
S = D
R = D‘
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40. SR To D FlipFlop Logic Ckt
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41. Applications of Flip-Flops
 These are the various types of flip-flops being used in digital electronic
circuits and the applications of Flip-flops are as specified below.
 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers
 Bounce elimination switch
 Data storage
 Data transfer
 Latch
 Registers
 Memory
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42. Registers
 One flip-flop can store one-bit of information. In order to
store multiple bits of information, we require multiple flip-
flops.
 The group of flip-flops, which are used to hold the binary
data is known as register.
 If the register is capable of shifting bits either towards right
hand side or towards left hand side is known as shift
register.
 An ‘N’ bit shift register contains ‘N’ flip-flops

43. Contd..
The four types of shift registers are.
1. Serial In − Serial Out shift register (SISO)
2. Serial In − Parallel Out shift register(SIPO)
3. Parallel In − Serial Out shift register(PISO)
4. Parallel In − Parallel Out shift register(PIPO)
Shift registers operations:
1. Shift left register
2. Shift right register

44. Serial In- Serial Out shift register
 It accepts data serially, one bit at a time on a single line,
and produces the sorted information on its output also in
a serial form
 Shift Right Register : The registers which will shift the
bits to Right are called “Shift Right registers”

47. Contd..
 Truth table
Din CLK Q1 Q2 Q3 Q4 Qout
Initial 0 0 0 0 0
1 1 1 0 0 0 0
1 2 1 1 0 0 0
1 3 1 1 1 0 0
1 4 1 1 1 1 1

48. Serial In- Serial Out shift register
 Shift Left Register :
The registers which will shift the bits to left are called
“Shift left registers”

49. Contd..
 Truth table
Din CLK Q4 Q3 Q2 Q1 Qout
Initial 0 0 0 0 0
1 1 1 0 0 0 0
1 2 1 1 0 0 0
1 3 1 1 1 0 0
1 4 1 1 1 1 1

50. Serial In- Parallel Out shift register(SIPO)
 Data bits are entered serially . Once the data are
stored, the output of each stage is available on its
output line.

51. Contd..
 Truth table
Input
Din
CLK Output
Q1 Q2 Q3 Q4
1 1 1 0 0 0
1 2 1 1 0 0
1 3 1 1 1 0
1 4 1 1 1 1

52. Parallel In- Serial Out shift register(PISO)
 The shift register, which allows parallel input (data is
given separately to each flip flop and in a
simultaneous manner) and produces a serial output
is known as Parallel-In Serial-Out shift register.

53. Parallel In- Serial Out shift register(PISO)

54. Contd..
 Truth table
Shif
t/Lo
ad
Input CLK Dout
a b c d
0 1 0 1 0 - -
1 X X X X 1 0
1 X X X X 2 1
1 X X X X 3 0
1 X X X X 4 1

55. Parallel In- Parallel Out shift register(PIPO)
The shift register, which allows parallel input (data is given separately
to each flip flop and in a simultaneous manner) and also produces a
parallel output is known as Parallel-In parallel-Out shift register.

56. Contd..
 Truth table
Input CL
K
Output
a b c d a b c d
1 0 1 0 1 1 0 1 0
1 0 1 1 2 1 0 1 1
0 1 0 0 3 0 1 0 0
1 1 1 1 4 1 1 1 1

57. ASYNCHRONOUS COUNTERS(Ripple Counters)
UP Counter

58. Down counter

59. SYNCHRONOUS COUNTERS

60. Synchronous, 4-bit up-down counter

61. S.NO SYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER
1.
In synchronous counter, all flip flops are triggered
with same clock simultaneously.
In asynchronous counter, different flip flops are
triggered with different clock, not simultaneously.
2.
Synchronous Counter is faster than asynchronous
counter in operation.
Asynchronous Counter is slower than synchronous
counter in operation.
3.
Synchronous Counter does not produce any
decoding errors.
Asynchronous Counter produces decoding error.
4.
Synchronous Counter is also called Parallel
Counter.
Asynchronous Counter is also called Serial Counter.
5.
Synchronous Counter designing as well
implementation are complex due to increasing the
number of states.
Asynchronous Counter designing as well as
implementation is very easy.
6.
Synchronous Counter will operate in any desired
count sequence.
Asynchronous Counter will operate only in fixed
count sequence (UP/DOWN).
7.
Synchronous Counter examples are: Ring
counter, Johnson counter.
Asynchronous Counter examples are: Ripple UP
counter, Ripple DOWN counter.
8. In synchronous counter, propagation delay is less.
In asynchronous counter, there is high propagation
delay.

62. Application of counters
 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.
241-208 CH9
62

63. Johnson counter and Ring counter.
63
 Shift registers can form useful counters by
recirculating a pattern of 0’s and 1’s. Two
important shift register counters are the Johnson
counter and the ring counter.
 The Ring counter and Johnson counter can be
made with a series of either D flip-flops or J-
K flip-flops.

64. Ring Counter
64
 The ring counter can also be implemented with either
D flip-flops or J-K flip-flops.
 4-bit ring counters are constructed from a series of D
flip-flops J-K flip-flops. Notice the feedback.
Initial status after
clear and Preset
Q0 Q1 Q2 Q3
0 0 0 1

65. Ring Counter
65
 A common pattern for a ring counter is to load it with a single 1 or a single
0.
 Draw the waveforms for the 4-bit ring counter ( shown in the previous
slide)

66. Johnson counter
66
 The Johnson counter is useful when you need a sequence that
changes by only one bit at a time but it has a limited number of
states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is initially
cleared are: CLK Q0 Q1 Q2 Q3
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
0
1
2
3
4
5
6
7
What are the remaining 3 states?

67. A Johnson counter is also known as switch-tail ring counter, twisted
ring counter, walking ring counter, or Möbius counter .
It is is a modified ring counter, where the output from the last stage is
inverted and fed back as input to the first stage.
The register cycles through a sequence of bit-patterns, whose length is
equal to twice the length of the shift register, continuing indefinitely.
These counters are useful in digital-to-analog conversion, generating
control signals etc.
In order to follow an ideal sequence of states both the Ring and the
Johnson counter must initially be forced into a valid state in the count
sequence using preset and clear inputs.

70. Thank You