Flip flops are basic digital memory elements that form the building blocks of sequential and combinational circuits. They have two stable states, logic 0 and logic 1. The document discusses different types of flip flops including latches, SR flip flops, D flip flops, JK flip flops, and T flip flops. It covers their triggering methods, excitation tables, state diagrams, and characteristic equations. Master-slave configuration is also described to avoid race-around conditions in flip flops.

1. Flip Flops
BY
SHASHI LATA
ASSISTANT PROFESSOR
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2. Flip Flops
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Flip- flop is a digital memory element which forms the
basic key component of any sequential or combinational
circuits in digital electronics. It has two stable states : logic
0 state and logic 1 state.

3. Contents
Combinational Circuits
Sequential Circuits
Latches
Triggering
Flip Flops
State Diagrams
Characteristic Equations
Excitation Tables
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4. Combinational Circuits
• Output depends only on the current input, doesn’t depends on past status of input.
• Has no memory.
• We don’t have any timing and synchronization signal such as clock signal.
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5. Sequential Circuits
• Output depends only on the current input, but also on past input values.
• To provide the previous input or output a memory element is required.
• The timing parameters also needs to be taken into consideration.
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6. www.advanced.edu.in
Sequential Circuits
Circuits that we
have learned
so far
Information Storing
Circuits
Timed “States”

7. 1-Bit Memory Cell
•Flip-Flops also known as basic digital memory circuit.
• Output of gate-1 is connected to the gate-2 and
output of gate-2 is connected to gate-1.
•Assume the output of gate-1 i.e. Q=1, hence R’=1.
As R’=1, output of gate2 i.e. Q’=0.
•This makes S’=0, hence Q continues to be =1.
•Similarly if we start with Q=0.
•This circuit has 2 stable states, one corresponds to
Q=1, Q’=0 and it is called as 1 state or set state.
•Whereas other corresponds to Q=0, Q’-1 and it is
called as 0stae or reset state.
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S’
R’
Q
Q’
0
1
1
0
1
2
Cross coupled inverter as memory
element

8. S-R Latch
•Cross coupled inverter is capable of locking or latching the information.
•Their disadvantage is that, we can’t enter the desired digital data into it.
•This disadvantage can be over come by modifying the circuit as below.
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Q
Q’
3
4
1
2
S
R

9. S-R Latch (NAND version)
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R
S
Q
Q’
0 0
0 1
1 0
1 1
S R Q Q’1
0
0
1
0 1 Reset
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND S=0, R=1 : Reset
Since S=0, it forces Q’ to be 1
Both inputs to NAND-1 are 1
Hence Q=0
Hence with S=0 & R=1, the outputs are Q=0 & Q’=1

10. S-R Latch (NAND version)
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R
S
Q
Q’
0 0
0 1
1 0
1 1
S R Q Q’1
1
1
0
Q Q’ No Change/Inactive
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Reset

11. S-R Latch (NAND version)
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R
S
Q
Q’
0 0
0 1
1 0
1 1
S R Q Q’0
1
1
0
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
Q Q’ No Change/Inactive
0 1 Reset
1 0 Set

12. S-R Latch (NAND version)
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R
S
Q
Q’
0 0
0 1
1 0
1 1
S R Q Q’1
1
0
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Inactive/No change
1 0 Reset
0 1 Set
1 0 Inactive/No change

13. S-R Latch (NAND version)
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R
S
Q
Q’
0 0
0 1
1 0
1 1
S’ R’ Q Q’0
0
1
1
0 0 1
0 1 1
1 0 1
1 1 0
X Y NAND
0 1 Inactive/No change
1 0 Reset
0 1 Set
1 0 Inactive/No change
1 1 Disallowed

14. Triggering Methods
Depending on which portion of clock signal the latch or flip flop responds to, classify them into
two types:-
1. Level Triggering.
2. Edge Triggering.
LEVEL TRIGGERING:-Circuit respond to change in their input, if their enable input(E) held at an
active level which may be steady high or low level .
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S Q
C
R Q’
S-R flip flop is enabled only when the
level is high
S-R flip flop doesn’t respond when the
level of clock signal is low

15. Types of Level Triggering Flip Flops
1. Positive Level Triggering :-Output of a flip flop respond to the input changes, only when its
clock inputs are high (1) level.
2. Negative Level Triggering :-Output of a flip flop respond to the input changes, only when its
clock inputs are low (0) level.
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The edge triggered flip flop samples the input at the
positive or negative edge and changes its outputs
accordingly
The level triggered flip flop output changes when clock
input is either at high or low level

16. EDGE TRIGGERING
Flip flops which changes their outputs only corresponding to the positive (rising) or negative
(falling) edge of the clock input.
Types of edge triggering:-
1. Positive edge triggering:-Flip flops which allows its output to change in response to its inputs
only at the instants corresponding to the rising edge of clock(positive spikes).Its output will
not respond to change in inputs at any other instant of time.
2. Negative edge triggering:-Flip flops which responds only to the falling edge of clock(negative
spikes) of the clock.
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17. Gated S-R Latch
(Level Triggered S-R Flip Flop)
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Disadvantage of S-R latch is that when S=R=0 or S=R=1 the outputs Q & Q’ either don’t change
or they are indeterminate (invalid).
Q changes only when clk (C)ic high(i.e. level sensitive).
S Q
C
R Q’

18. D Latch
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To eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are
never 1 simultaneously. This is done in the D latch:
D Q
C
Q’

19. J-K Latch
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Q
Q’
3
4
1
2
J
K
C
C J K Next state of Q
0 x x Q No Change
1 0 0 Q No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q' Toggle
J Q
C
K Q’

20. Race – around condition
If inputs of J-K flip-flop are J=K = 1, and Q= 0 and clock pulse as shown in figure,
after a time interval Tp equal to propagation delay of NAND gates, the output
will change to Q=1. now, we have J=1, K=1 and Q=1. if duration of clock pulse (T)
is greater than propagation delay, Tp , after another time interval of Tp the
output will change back to Q=0, hence the output will oscillate back and forth
between 0 and 1. the output is uncertain at the end of clock pulse if flip-flop is
level trigger. This situation is called race-around condition.
The race-around condition can be avoided if clock pulse is reduced than the
propagation delay of flip-flop, i.e., t<Tp<T, but this is not practically feasible. A
more practical method for this is the use of master-slave flip-flop.
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21. Race – around condition
Output is
uncertain
Clock
pulse
0
t T
Tp
output
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22. Flip Flops
Latches are “transparent” (=any change on the inputs is seen at the outputs immediately when
c=1).
This causes synchronization problems.
This problem can be removed by cg latch to create flip flops that can respond(update) only on
specific times (instead on any time).
Flip flops are said to be edge sensitive or edge triggered rather than level triggered .
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23. S-R Flip Flop
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Q
Q’
3
4
1
2
S
C
CLK
R1 R2
D
R
C S R Next stage of Q
0 x x No Change
1 x x No Change
x x No Change
0 0 No Change
0 1 Reset
1 0 Set
1 1 Invalid
S Q
C
R Q’

24. D Flip-Flop
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Q
Q’
3
4
1
2
SC
CLK
R1 R2
D
R
C D Next stage of Q
0 x No Change
1 x No Change
x No Change
0 Q follows D input
1 Q follows D input
D Q
C
Q’

25. J-K Flip-Flop
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Q
Q’
1
2
3
4
J
K
S
C
CLK
R1 R2
D
Q
Q’
R
C J K Next stage of Q
0 x x No Change
1 x x No Change
x x No Change
0 0 No Change
0 1 Reset
1 0 Set
1 1 Toggle
J Q
C
K Q’

26. Toggle Flip-Flop(T Flip-Flop)
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J Q
C
K Q’
T
C T Next stage of Q
0 x No Change
1 x No Change
x No Change
0 No Change
1 Toggle
Toggle flip-flop output toggles on clock edge
Toggle flip-flop is basically a J-K flip-flop with J & K terminals permanently
connected together.

27. Master-Slave FF Configuration Using S-R
Latches
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S
C
R
S
C
R
S
C
R
Y
Y’
Q
Q’

28. Master-Slave FF Configuration Using S-R
Latches
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C S R Q Q' Next stage of Q
0 x x Q Q' No Change
1 0 0 Q Q' No Change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 1 1 Invalid
When C=1, master is enabled and stores new data, slave
stores old data.
When C=0, master’s state passes to enabled state,
master not sensitive to new data (disabled)

29. State Diagrams: D
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◦ The D flip-flop has the following state table
◦ Note that changes on clock edge are always assumed
◦ The corresponding state diagram is
◦ Again, transitions occurs only on a clock edge
D Q(t+1)
0 0
1 1
0 1 1
0
0
1
Q(t+1) = D
D
Q
0 1
0 0 1
1 0 1
characteristic
equation

30. State Diagrams: T
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The T flip-flop state table
The state diagram is
0 1 0
1
0
1
Q(t+1) = TQ(t)' + T'Q(t) = T  Q(t)
T Q(t+1)
0 Q(t)
1 Q(t)'
T
Q
0 1
0 0 1
1 1 0
characteristic
equation

31. State Diagrams: S-R
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The SR flip-flop state table
The state diagram is
0 1 x0
01
0x
10
Q(t+1) = S + R'Q(t)
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 x
S R
Q
00 01 11 10
0 0 0 x 1
1 1 0 x 1
characteristic
equation

32. State Diagrams: J-K
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The JK flip-flop state table
The state diagram is
0 1 x0
x1
0x
1x
Q(t+1) = J Q(t)' + K' Q(t), or
Q(t+1) = J Q(t)' + K' Q(t) + J K'
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)'
J K
Q
00 01 11 10
0 0 0 1 1
1 1 0 0 1
static hazard!!
characteristic
equation

33. Characteristic Equations
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Summary of the characteristic equations
How is the next state determined from the inputs and current state?
Flip-flop Characteristic Equation
D Q(t+1) = D
T Q(t+1) = T  Q(t)
SR Q(t+1) = S + R' Q(t)
JK Q(t+1) = J Q(t)' + K' Q(t)

34. Excitation Tables
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Summary of the excitation tables
For each state transition Q(t)  Q(t+1), what input combination(s) will
produce that transition?
Q(t) Q(t+1) D T SR JK
0 0 0 0 0x 0x
0 1 1 1 10 1x
1 0 0 1 01 x1
1 1 1 0 x0 x0

35. Conclusion
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•Flip – flops can be used as a memory element and also as a delay
element.
•Flip – flops are also used in the making of counters/timers.
•Using Flip – flops, we can eliminate keyboard debounce.
•In various type of registers also we use flip –flops.

36. SHASHI LATA
ASSISTANT PROFESSOR
shashi_fbd@rediffmail.com
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