A demultiplexer (DEMUX) is a digital switch that takes a single input and routes it to one of multiple outputs based on select lines. A 1-to-4 DEMUX has one input, two select lines, and four outputs, allowing the input to be routed to one of the four outputs. DEMUXs are commonly used to route a single source to multiple destinations, like routing a data signal to different devices. Sequential circuits use flip-flops and a clock signal to change states at discrete time intervals. Common types of flip-flops include SR, JK, D and T flip-flops, which differ in their number of inputs and how the inputs affect the output state. A

1. Unit-2
Flip flop and De-Mux

2. What is a Demultiplexer (DEMUX)?
• A DEMUX is a digital switch
with a single input (source) and
a multiple outputs
(destinations).
• The select lines determine
which output the input is
connected to.
• DEMUX Types
 1-to-2 (1 select line)
 1-to-4 (2 select lines)
 1-to-8 (3 select lines)
 1-to-16 (4 select lines)
2
Demultiplexer
Block Diagram
Select
Lines
Input
(source)
Outputs
(destinations)
2N
1
N
DEMUX

3. Typical Application of a DEMUX
3
Single Source Multiple Destinations
Selector
D0
D1
D2
D3
X
DEMUX
B A Selected Destination
0 0 B/W Laser Printer
0 1 Fax Machine
1 0 Color Inkjet Printer
1 1 Pen Plotter
B/W Laser
Printer
Color Inkjet
Printer
Pen
Plotter
Fax
Machine

4. 1-to-4 De-Multiplexer (DEMUX)
4
B A D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
D0
D1
D2
D3
X
B A
DEMUX

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Sequential Circuits
• Synchronous sequential circuits employ
signal that affect the storage elements only at
discrete instant of time.
• Synchronization is achieved by a timing
device called a clock pulse generator that
produces a periodic train or clock pulses.
• The storage elements employed in clocked
sequential circuits are called flip-flop.

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Sequential Circuits
• As the name implies, sequential logic circuits require
a means by which events can be sequenced.
• State changes are controlled by clocks.
– A “clock” is a special circuit that sends electrical pulses
through a circuit.
• Clocks produce electrical waveforms such as the
one shown below.

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3.6 Sequential Circuits
• State changes occur in sequential circuits only
when the clock ticks.
• Circuits can change state on the rising edge,
falling edge, or when the clock pulse reaches its
highest voltage.

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3.6 Sequential Circuits
• Circuits that change state on the rising edge, or
falling edge of the clock pulse are called edge-
triggered.
• Level-triggered circuits change state when the
clock voltage reaches its highest or lowest level.

10. Definition of Latch
• A latch is an electronic logic circuit that has
two inputs and one output. One of the inputs
is called the SET input; the other is called
the RESET input.
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11. Latch
• Latch circuits can be either active-high or active-
low. The difference is determined by whether the
operation of the latch circuit is triggered by HIGH
or LOW signals on the inputs.
• Active-high circuit: Both inputs are normally tied
to ground (LOW), and the latch is triggered by a
momentary HIGH signal on either of the inputs.
• Active-low circuit: Both inputs are normally
HIGH, and the latch is triggered by a momentary
LOW signal on either input. 11

12. Active-high circuit
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13. Active-low circuit
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14. Flip flop
• A Flip flop is a binary cell capable or
storing one bit or information
• It has 2 outputs , zero & one;
• A flip-flop maintains a binary state until its
directed by a clock pulse to switch states.
• The difference among various types or FF is
in the no of inputs they posses and in the
manner in which the inputs affect the binary
state.
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15. FF
• Flip-flops can be divided into common types:
• SR Flip Flop : Set/Reset Flip Flop
• D Flip Flop : Data Flip Flop to store Bit
• J‐K Flip Flop: SR with use of the
unavoidable SR=11 state to Toggle
• T Flip Flop: Toggle Flip Flop
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3.6 Sequential Circuits
• SR flip-flop.
– The “SR” stands for set/reset.
• The internals of an SR flip-flop (latch) are shown below,
along with its block diagram.
• Arrow head shaped symbol is front of the letter C to
designate a dynamic i/p. It denotes that the FF responds to
a positive transition (from 0 to 1) of the i/p clock signal

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3.6 Sequential Circuits
• The behavior of an SR flip-flop is described by
a characteristic table.
• Q(t) means the value of the output at time t.
Q(t+1) is the value of Q after the next clock
pulse.

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3.6 Sequential Circuits
• The behavior of an SR flip-flop is described by
a characteristic table.
• Q(t) means the value of the output at time t.
Q(t+1) is the value of Q after the next clock
pulse.

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3.6 Sequential Circuits
• The SR flip-flop actually
has three inputs: S, R,
and its current output, Q.
• Thus, we can construct
a truth table for this
circuit, as shown at the
right.
• Notice the two undefined
values. When both S
and R are 1, the SR flip-
flop is unstable.

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3.6 Sequential Circuits
• The SR flip-flop can be modified to provide a
stable state when both inputs are 1.
• This modified flip-flop is
called a JK flip-flop,
shown at the right.
- The “JK” is in honor of
Jack Kilby.

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3.6 Sequential Circuits
• At the right, we see
how an SR flip-flop
can be modified to
create a JK flip-flop.
• The characteristic
table indicates that
the flip-flop is stable
for all inputs.

22. • J input is equivalent to the S(set) input of
the SR and the K input is equal to the R
(Clear) input.
• Instead of the indeterminate condition the
JK flip flop has a complement condition
Q(t+1)=Q’(t) when both JK=1;
22

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3.6 Sequential Circuits
• Another modification of the SR flip-flop is the D flip-
flop, shown below with its characteristic table.
• An SR FF is converted to a D FF by inserting an
inverter between S and R and assigning the Symbol
D to the single input.
• If D=1,the o/p of the FF goes to 1; If D=0,the o/p of
the FF goes to 0;

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3.6 Sequential Circuits
• The D flip-flop is the fundamental circuit of
computer memory.
– The advantage of D FF is only one i/p;
– The disadvantage is doesn’t have “No change”
condition
Q(t+1)=Q(t)

25. Sequential Circuits
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26. • T FF ,obtained by inputs J and K connected
to provide a single i/p designated by T.
• When T=0( J=K=0) a clock transition does
not change the state of the FF;
• When T=1( J=K=1) a clock transition does
complements the state of the FF;
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27. Master Slave Flip Flop
• Consist of two Flip-flops. First responds to
the positive level of the clock(Master),The
second (Slave) which responds to the
negative level of the clock.
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