The document discusses Field Programmable Gate Arrays (FPGAs) and compares them to Application-Specific Integrated Circuits (ASICs), highlighting advantages such as quick configuration and reconfigurability, and disadvantages like larger space requirements and slower performance compared to ASICs. It also details the architecture of FPGAs, including components such as configurable logic blocks and input/output blocks, and identifies two types of FPGAs: reprogrammable and one-time programmable. Additionally, it touches on Actel FPGAs, emphasizing their multiplexer-based logic cells and various logic modules.

1. ACTEL FPGAs
Dr. D. V. Kamath
Professor, Department of E&C Engg.,
Manipal Institute of Technology, Manipal
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FPGAs
 FPGAs are pre-fabricated silicon devices that can be
electrically programmed to implement any digital system
 Important characteristics of FPGAs (Field Programmable Logic
Devices) are as follows:
• Customized by end user
• Implements multi-level logic function
• Fast time to market and low risk

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FPGAs
 Advantages of FPGAs:
• Configuring a FPGA using a hardware description language
(HDL) is faster than developing an ASIC
• Easy design upgradation using FPGA due to its reconfigurability
• FPGAs are perfect choice for rapid prototyping of digital circuits
Disadvantages of FPGAs:
• FPGA needs more space (transistors) on chip as compared to the
ASIC counterpart for the same application
• The application runs slower on a FPGA when compared with its
ASIC counterpart

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FPGAs and ASICs
ASIC FPGA
• Designs must be sent for
expensive and time consuming
fabrication in semiconductor
foundry
• FPGAs can be bought off the shelf
and reconfigured by designers
themselves
• Designed all the way from
behavioral description to physical
layout
• No physical layout design; design
ends with a bitstream used to
configure a device
• Low cost in high volumes • Low development cost
• High performance • Reconfigurability and short time to
market

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FPGA architecture
 An FPGA consists of a large number of configurable logic cells.
Each logic cell can be configured to implement a certain set of
function.
 Each logic cell has a fixed number of inputs and outputs.
 Basic building blocks in FPGA architecture are
• CLB Configurable logic block
• IOB Input/ Output block
• Interconnect : connection between CLBs and between CLBs
and IOBs

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FPGA
General structure of an FPGA

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FPGAs
Two types of FPGAs
 Reprogrammable FPGA
Uses memory based logic cells
Uses sRAM configuration cell
Vendors : Xilinx , Lattice, Atmel, Altera
 One-time Programmable(OTP) FPGA
Uses multiplexer based logic cells
Antifuse switch based
Vendors : Actel, Quicklogic
Xilinx Inc. and Altera Corp. share 60% of the FPGA market.

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2-input MUX as programmable logic block
F
A 0
B
S
1
Configuration
A B S F=
0 0 0 0
0 X 1 X
0 Y 1 Y
0 Y X XY
X 0 Y
Y 0 X
Y 1 X X + Y
1 0 X
1 0 Y
1 1 1 1
XY
XY
X
Y

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Multiplexer logic as function generator
 Shannon’s Expansion Theorem
Let a function F(a, b, c) is expanded with respect to a, then F can
be expressed as
𝐹 = 𝑎 . 𝐹𝑎 +𝑎 . 𝐹𝑎
where 𝐹𝑎 = F/a = 1 and 𝐹𝑎 = F/a = 0
 Implementation of two-level combinational function using
multiplexers

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Multiplexer logic as function generator
Shannon’s Expansion Theorem
 The function can be recursively or simultaneously expanded with
respect to two or three variables.
𝐹 = 𝑎. 𝑏 . 𝐹 𝑎 𝑏 +𝑎. 𝑏 . 𝐹𝑎 𝑏 + a. 𝑏 . 𝐹 𝑎𝑏 + a.b . 𝐹𝑎𝑏
 Implementation of multi-level combinational function using muxs

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ACTEL FPGAs
 ACTEL FPGA uses multiplexer based logic cells
 The multiplexer-based logic module is typically composed of a
tree of 2-to-1 MUXes.
 Different types of Logic Modules(LMs) available are :
ACT 1 LM
ACT 2 - C, ACT 2 - S
ACT 3 - C, ACT 3 - S

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ACTEL FPGAs
ACTEL ACT1 Logic module (LM)

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ACT 1 Logic Module (LM)
Implementation of combinational function using ACT1 Logic Module (LM)

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ACT-2 C-Module
ACTEL ACT2 Combinational Logic module (LM)

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ACT 2 S-Module
ACT2 Sequential Logic module (LM)

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ACT 3 S-Module
ACT3 Sequential Logic module (LM)

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ACT 2 S-Module
Internal circuit of SE(sequential element)

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SE can be configured as a positive edge triggered D flip-flop by Selecting 𝐶1 = 0
and 𝐶2 = CLK

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ACT 2 S-Module
SE configured as a positive edge triggered D flip-flop

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• dv.kamath@manipal.edu
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