Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain programmable logic components and programmable interconnects. FPGAs can be reprogrammed to desired functionality requirements after manufacturing. The document discusses the building blocks of FPGAs, including configurable logic blocks (CLBs), interconnects, input/output blocks, block RAM, digital signal processing slices, and clock management resources. It also covers FPGA routing architectures and common FPGA design flows.

1. Field Programmable Gate
Arrays
Building Blocks and Routings
Dr. U. Saravanakumar
Associate Professor
Department of ECE
Anna University Sponsored Faculty Development Programme on VLSI Design at
Vel Tech Multi Tech Engineering College, Chennai on 13.12.2017

2. Outline
• Introduction to Integrated Circuits
• ASICs
• PLDs
• FPGAs introduction
• Why FPGAs
• Building Blocks
• FPGA Routings
• Clocking
• Embedded cores for FPGAs
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3. Integrated Circuits
Integrated Circuits (ICs)
Application Specific
ICs
User Programmable
Programmable Logic
Devices (PLDs)
Field Prog. Gate
Arrays (FPGAs)
Semi Custom Full Custom
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4. IC - ASIC
• Simple Gate ICs to High Performance Processor ICs.
• Example: 2 – Input NAND Gate ICs Apple A6 ASIC
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5. PLDs
Types
• Programmable Read Only Memories (PROMs)
• Programmable Logic Arrays (PLAs) – Soln to the problems of PROMs
• Programmable Array Logic (PALs)
• Complex Programmable Logic Devices (CPLDs)
• Field Programmable Gate Arrays (FPGAs)
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6. PROMs
• Programmable Read Only Memories (PROMs)
• Can be programmed by the user to a specific pattern
• Limited I/Os
• For Seq. FFs must be added
• Slow
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7. PLAs
• Replacement for the PROM’s are programmable logic devices or in short PLA.
• PLA is a circuit that allows implementing Boolean functions in sum-of-product form.
• The typical implementation consists of programmable AND-matrix followed by the
programmable OR-matrix.
• The input lines run horizontally into the AND matrix, while the so-called product-term
lines run vertically. Therefore, the size of the AND matrix is twice the number of inputs
times the number of product-terms.
Draw Backs:
1. Expensive
2. Poor Speed – Performance
Reason: 2 – level programmable logic
planes were difficult to manufacture and
introduced significant propagation delays Dr. U. Saravanakumar 7

8. PALs
• Soln to the problems of PLAs
• Programmable AND array
• Fixed OR Array
• Example: 4 – Input and 3 – Output
Example:
f1 = y’z + xy’ + xz + x’yz’
f2 = x’y’ + z
f3 = xy’ + xz
f1 = y’z + f3 + x’yz’
Often Called Simple PLD (SPLD)Dr. U. Saravanakumar 8

9. CPLDs
• Higher capacity than SPLDs
• High Chip density (Only Logically)
• Can be treated as multiple PLDs + Prog. interconnection in a single chip
• Either more logical functions / more complicated function
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10. Gap B/W PLDs and ASICs
Xilinx identified this gap and introduced new type of IC, called Field Programmable Gate Array (FPGA)
The first FPGAs were based on CMOS and used SRAM cells for configuration purposes
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11. FPGAs
• FPGAs are semiconductor devices that are based around a matrix of configurable logic
blocks (CLBs) connected via programmable interconnects.
• FPGAs can be reprogrammed to desired application or functionality requirements after
manufacturing.
• This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom
manufactured for specific design tasks.
• Although one-time programmable (OTP) FPGAs are available, the dominant types are
SRAM based which can be reprogrammed as the design evolves.
Field Programmable Gate Array
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12. FPGAs
• The early devices were based on the concept of a programmable logic block, which
comprised a 3-input lookup table (LUT), a register that could act as a flip-flop or a latch,
and a multiplexer, along with a few other elements that are of little interest here.
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13. Why FPGAs?
• Designing with FPGA: Faster, Cheaper
• Ideal for customized designs
• Product differentiation in a fast-changing market
• Offer the advantages of high integration
• High complexity, density, reliability
• Low cost, power consumption, small physical size
• Avoid the problems of ASICs
• high NRE cost, long delay in design and testing
• increasingly demanding electrical issues
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14. Why FPGAs?
• Very fast custom logic
• massively parallel operation
• Faster than microcontrollers and microprocessors
• much faster than DSP engines
• More flexible than dedicated chipsets
• allows unlimited product differentiation
• More affordable and less risky than ASICs
• no NRE, minimum order size, or inventory risk
• Reprogrammable at any time
• in design, in manufacturing, after installation
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15. Field Programmable Device
Field Programmable Devices (FPD) consist of,
• Basic Section of FPD:
• Logical Block (CLB: LUT, Mux, Gates and Flip-flops)
• Routing (Switch Matrix)
• Input Output Block
• More Advanced FPD Contains:
• On-chip Memory (as BRAMs)
• Embedded Processor
• Clock Management (PLL/DLL)
• High-Speed Transceiver
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16. Commercial FPGAs
• Xilinx
• FPGAs: Spartan, Virtex, Kintex, Artix
• SoC: Zynq (Processors: Zynq, Microblaze)
• Intel FPGA
• FPGAs: Stratix, Arria, Cyclone, Max
• SoCs: Stratix 10, Arria 10, Cyclone V (Processor: Nios II)
• Lattice Semiconductor
• FPGAs: iCE, MachXO
• Microsemi
• FPGAs: Polarfire, IGLOO2, RT-FPGA
• SoCs: Smart Fusion
Leaders
Small Stakeholders
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17. Types of FPGAs
• Reprogrammable (SRAM based – Pass Transistor)
• One Time Programmable FPGAs (Anti Fusing)
• EEPROM based FPGA
SRAM Based FPGA
Anti Fuse
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18. FPGA Structures
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19. FPGA Structures
Building Blocks of FPGAs
• Configurable Logic Blocks
• Switch and Interconnections
• IO Blocks
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20. Logic Blocks FPGAs
Example: y = (a & b) | c’
Internal Structure of Logic Block
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21. Size of the Logic Blocks
• Coarse grain
• Owing to SRAM interconnection area (6 transistors) the Logic Blocks are made large
in SRAM based FPGA
• Utilization is made high with configurability with in the logic block
• Fine Grain
• Since the antifuse occupies less area and has less time delay, antifuse based FPGA’s
employs smaller size logic blocks
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22. Logic Block - Coarse Grain
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23. Logic Block - Fine Grain
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24. Realization of Logic Blocks
• Mux Based
• LUT Based
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25. Realization of Logic Blocks – Mux Based
• Mux Based – Block contains only MUX
• Consider the example: y = (a & b) | c
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26. Realization of Logic Blocks – LUT Based
• LUT Based – Simple
• Example: y = (a & b) | c
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27. LUT Based CLB
• LUT based CLBs are the best choice.
• Why?
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28. LUT Based CLB
The reason is
• …it was possible to achieve the best results using MUX-based architectures.
• It is also said that MUX-based architectures have an advantage when it comes to
implementing control logic along the lines of “if this input is true and this input is false,
then make that output true ...”
• However, some of these architectures don’t provide high-speed carry logic chains, in
which case their LUT-based counterparts are left as the leaders in anything to do with
arithmetic processing
• Eg: Telecommunication and Networking areas
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29. Xilinx CLB – Logic Cell
• Core building block is called
Logic Cell (LC)
• It consist of 4-input LUT,
MUX and Register
• Polarity of the clock can be
configured.
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30. Altera LAB – Logic Element
• Core blocks are called as
Logic Elements
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31. Xilinx / Altera
• Hierarchy should be followed
to provide better
trade off
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32. Distributed RAMs and Shift Registers
From the previous, the CLB can be treated as,
• Single-port 16 × 8 bit RAM OR
• Single-port 32 × 4 bit RAM
• Single-port 64 × 2 bit RAM 4 – input LUT can be configured
• Single-port 128 × 1 bit RAM as 16 – bit SR and the CLB
• Dual-port 16 × 4 bit RAM can be configured as 128 bit SR
• Dual-port 32 × 2 bit RAM
• Dual-port 64 × 1 bit RAM
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33. Embedded RAMs
• A lot of applications require the use of memory, so FPGAs
now include relatively large chunks of
embedded RAM called e-RAM Or
block RAM
• Each e-RAM can be used independently,
or multiple blocks can be combined
together to implement larger blocks.
These blocks can be used for a variety of
purposes, such as implementing standard
single- or dual-port RAMs, first-in
first-out (FIFO) functions, state machines, and so forthDr. U. Saravanakumar 33

34. And then….
• Additionally Multipliers, adders, MAC,…
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35. Embedded Processor too…
• High-end FPGAs have become available that contain one or more embedded
microprocessors, which are typically referred to as microprocessor cores
• Types:
• Hard
• Soft
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36. Embedded Processor too…
Hard Core
Multi Chip Module Single ChipDr. U. Saravanakumar 36

37. Embedded Processor too…
• Soft core
• It is possible to configure a group of programmable logic blocks to act as a
microprocessor.
• These are typically called soft cores, but they may be more precisely categorized as
either “soft” or “firm.
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38. FPGA Routing
• Connection Boxes
• Switch Boxes
• Single length lines
• Double length lines
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39. FPGA Routing
• Connection Boxes
• Switch Boxes
• Single length lines
• Double length lines
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40. FPGA Routing
• The whole…
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41. Clocking
All of the elements inside the FPGA are synchronous.
• The registers configured to act as flip-flops inside the programmable logic blocks—need
to be driven by a clock signal.
• Such a clock signal typically originates in the outside world, comes into the FPGA via a
special clock input pin, and is then routed through the device and connected to the
appropriate registers.
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42. Clock trees
• The main clock signal
branches again and again
(the flip-flops can be consider,
to be the “leaves” on the
end of the branches).
• Clock skew will appear, if the clock is
distributed as a long wire.
• Unused clock pins can be
employed as general-purpose I/O pin
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43. Clock Managers
• A clock manager that generates a number of daughter clocks.
In Xilinx architecture, it is referred as Digital Clock Manager (DCM)
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44. Clock Managers
• These daughter clocks may be used to drive internal clock trees or external output pins
that can be used to provide clocking services to other devices on the host circuit board.
• Each family of FPGAs has its own type of clock manager (there may be multiple clock
manager blocks in a device), where different clock managers may support only a subset
of the following features:
• Jitter removal
• Frequency synthesis
• Phase Shifting
• Auto-Skew Correction
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45. Clock Managers
• Jitter Removal
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46. Clock Managers
• Frequency Synthesis
• Phase Shifting
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47. Clock Managers
• Auto – Skew Correction
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48. Clock Managers
Clock managers can be designed using
• Phase Locked Loops (PLL) – Can be implemented using either Analog or Digital
techniques.
• Digital Delay Locked Loops (DLL ) – Can be implemented using only digital.
• offer advantages in terms of precision, stability, power management, noise insensitivity, and
jitter performance
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49. General Purpose I/O
• Today’s FPGA packages can have more than 1,000 pins, which are arranged as an array
across the base of the package.
• When it comes to the silicon chip inside the package, flip-chip packaging strategies allow
the power, ground, clock, and I/O pins to be presented across the surface of the chip.
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50. Configurable I/O Standards
• FPGA’s general-purpose I/O can be configured to accept and generate signals conforming
to whichever standard is required.
• These general-purpose I/O signals will be split into a number of banks
• Assume eight such banks numbered from 0 to 7
each bank can be configured individually to support
a particular I/O standard
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51. Supply Voltages
• Core Vs. I/O
• Voltage value: 5 V to < 1.2 V
• Core: The geometries of the structures on silicon chips became smaller because smaller
transistors have lower costs, higher speed, and lower power consumption. However,
these processes demanded lower supply voltages, which have continued to fall over the
years.
• The point is that, the supply is used to power the FPGA’s internal logic.
• I/O: However, different I/O standards may use signals with voltage levels significantly
different from the core voltage, so each bank of general-purpose I/Os can have its own
additional supply pins.
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52. Gigabit transceivers
• The traditional way to move large a mounts of data between devices is to use a bus.
• Early 1975’s: 8 – bit
• Now: 16, 32, 64, 128…
• Issues: More number of bus tracks & Signal Integrity
• Solution: Hard wired gigabit transceiver blocks
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53. Design Flows
• Schematic based design flow
• HDL based design flow
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54. Design Flows - Schematic
• Design Entry: Schematic
• Target: FPGA
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55. Design Flow- HDL
• Design Entry: Text
• Target: FPGA
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56. Design Flow – Multi level
• Top Module – Text / Schematic
• Sub – Modules:
• State diagram
• Text
• GUI
• Block level schematic
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57. Complete Design Flow
• For Xilinx (Can be used for others)
• HDL – Verilog / VHDL
• Isim – Simulation – Functional and
Timing
• XST – Synthesis
• FPGA – Xilinx / Altera….
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58. Programming Languages
• HDL – Verilog / VHDL
• System C
• System Verilog
• C / C++
• MatLab / Simulink
• LabVIEW
• Handle C / Open CL
• Now Python also – Suitable H/W – Pynq Z1 from Digilent
Dominant Languages
Xilinx
High level
Synthesis tool
is supporting
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59. Software
• Xilinx – ISE /VIVADO
• Altera – Quartus II
• Lattice – ICE CUBE / Diamond can be used for
• Microsemi simulation +
• Icarus – Open Source synthesis
• Edaplayground.com – web based simulator
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60. At Present…
• Xilinx 7 Series FPGAs
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61. At Present..
• The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs)
with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but
common addresses or logic inputs.
• Each LUT output can optionally be registered in a flip-flop.
• Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic
form a slice.
• Two slices form a configurable logic block (CLB).
• Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches.
• Each 7 series FPGA has up to 24 clock management tiles (CMTs), each consisting of one
mixed-mode clock manager (MMCM) and one phase-locked loop (PLL).
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62. At Present
• Xilinx 7 Series
CLB
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63. And more features…
• IC: Zynq
• Boards:
• ZYBO
• Zedboard
• Picozed
• Microzed
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64. Finally…
Single gate to System on Chip
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65. Books to Read
• “FPGA-Based System Design” by Wolf
• “Digital Systems Design with FPGAs and CPLDs” by Ian Grout
• “Digital System Designs and Practices: Using Verilog HDL and FPGAs” by Ming-Bo Lin
• “Design Recipes for FPGAs: Using Verilog and VHDL” by Peter Wilson
• “Advanced FPGA Design: Architecture, Implementation, and Optimization” by Steve Kilts
• “Verilog HDL” by Samir Palnitkar
• “VHDL : Programming By Example” by Douglas L. Perry
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66. FPGA Accelerators for…
• Networking
• Biomedical
• Data Centers
• Defence
• Space
• Multimedia – Audio / Video …
• IOT
• And more… the list is endless…
Migration towards
Reprogrammable…
Reconfigurable…
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67. One example is enough…
• Apple
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68. Thank You!
Dr. U. Saravanakumar 68