The document discusses trends and challenges in IP-based SoC design, highlighting modern design considerations such as power management, multi-processor systems, and reconfigurable logic. It emphasizes the necessity for testability and verification while addressing future challenges like embedded memory and network-on-chip architectures. The conclusion advocates for packet-switched networks-on-chip as a solution to complex SoC interconnect issues, projecting advancements in quality-of-service, fault-tolerance, and secure communication.

1. Trends and Challenges in IP
based SoC design
AISHWARYA R (17BEC045)
Department of Electronics and Communication Engineering,
Kumaraguru College of Technology.

2. INTRODUCTION:
 The technology revolution has had a profound impact on our daily life. The annual
growth rate is about 2 faster than general-purpose microprocessors.
 Such a change is largely due to the advances in device technology, which enable
us to put billions of transistors on a chip for almost unlimited processing capability.
 The first microprocessor had a couple of thousand transistors with functionalities
limited to basic logic/arithmetic processing. In contrast, a modern SoC can have
billions of transistors, supporting a wide range of functions (processors/ controllers,
application-specific modules, data storage, and mixed-signal circuits).

3. Modern Design Trends:
 Power management
 MPSoC
 Reconfigurable logic
 Design for testability/ verification

4. Power management
 Power dissipation is one of the primary design considerations. In particular, transistor
dissipation is not falling at the same rate as the gate density is increasing. Rather than
on processor technology, modern designs start addressing the problem at the circuit level
and the architecture level.
 One can reduce system-level power dissipation by shutting off parts of the system that are
not used and turning those parts back on when requests have to be serviced (or reduce
increase the voltage and frequency).
 Another important technique to reduce power consumption is to reduce power
of clock distribution.

5. Multi-Processor SoC
 To further increase performance without substantially increasing power
consumption parallel processing can be used at the instruction level (e.g., VLIW
[27]) and at the data level (e.g., SIMD [65]).
Reconfigurable logic
 To create high-performance, versatile platforms, some architectures start
logic operations and interconnects that can be reconfigured during run time.
 Adding reconfigurable logic to the SoC provides flexibility for changing functionality
after fabrication. Compared to programmable processors, these architectures offer the
potential to achieve higher performance and power-efficiency with greater flexibility.
 To boost the impact of reconfigurable SoCs, some research work has been done to
extract the parallelism from the applications/ algorithms and map the parallelism into
reconfigurable architecture efficiently.

6. Design for testability/ verification
 IP providers and SoC integrators must work closely together to define
effective test strategies. Each IP block must have a wrapper so that it can
be isolated from other parts of the system while it is being tested .
 Design for testability (DFT) is an important practice which provides means
to comprehensively test a manufactured SOC for quality and coverage.
Failures to detect flaws in fabrication before putting a chip to service can
be disastrous and often fatal.

7. Future Challenges:
 Embedded memory
 Network-on Chip
 Reliability
 Scalable & reusable architecture

8. Scalable or Reusable Architecture
 To ensure fast design turnaround time without completely redesigning the whole system, a
architecture is highly desired.
 Just as we shifted our IC design paradigm from full custom design to standard cells, even to IP
reuse, the next-generation system design paradigm shift should be the reuse of architecture. That
to cope with the growing complexity of SoCs, IP reuse may not be enough.
 Reuse must happen at a much higher level than it used to, e.g., architecture reuse [25]. However,
creating a design that can be efficiently reused requires a great deal of effort.
Network-on-Chip
 While many communication architectures make use of buses or crossbars, there are some recent
proposals on network-on-chip (NoC) architectures.
 One approach is to employ a packet-switched interconnect. The concept is similar to traditional
large-scale wide-area networks, but in this case, onchip router-based networks are used.

9. Embedded Memory
 Embedded memory (SRAM, DRAM, flash, ROM) will be integrated onto the chip. The amount of
memory integrated into an ASIC-type SoC design has increased from 20%.
 Challenges arise when trying to balance efficiency and power. SRAM provides high performance,
while flash memory is the best solution in terms of power consumption. The amount and the
placement of each kind of memory in the SoC will greatly affect access efficiency and power.
Reliability
 Reliability is likely to be a major focus of research as we approach the end of the decade. As
transistor sizes become smaller than 20 nm, we are likely to see increasing variability in the
behavior of the transistors .
 Smaller feature sizes lead to more failures over time from electrostatic overstressing and electro-
migration. While transistors might fail, the entire system cannot fault. We must explore
mechanisms to compensate for this underlying variability in transistor behavior.

10. Challenges in SoC Era :
Design Complexity :
 Cs, DSPs, HW/SW, SW protocol stacks, RTOS’s, digital/analog IPs, On-chips buses
 System-level architecture
Time-in-market :
 Performance/Energy/Cost tradeoff
 Scalable architecture with unified design environment
Time-to-market :
 Process roadmap acceleration
 Consumerization of electronic devices
Silicon Complexity:
 Heterogeneous processes
 Billion Transistors, Deep submicron effects : crosstalk, wire delays, electromigration,
mask costs

11. How to Conquer the Complexity?
Use a known real entity
 A pre-designed component (IP reuse)
 A platform (architecture reuse)
Partition
 Based on functionality
 Hardware and software
Modeling
 At different level
 Consistent and accurate

12. IP
A predefined, designed/verified, reusable building block for System-on-Chip
.Software IP, Silicon IP (Soft IP, Hard IP, …)
IP types :
 Foundation IP (cell library, gate array)
 Standard IP (MPEG2/4, JPEG, USB, IEEE 1394, PCI…)
 Star IP (ARM, MIPS, Rambus, …)
Ancillary characteristics :
 Deliverable at certain level, software/hardware interfaces
 Modeling at different levels
 Customizable, Configurable, Parameterizable

13. Challenges for CAD Tools in IP-based SoC Design
 Designing at higher levels of abstraction
 Verification
Better and faster verification
 Timing & Power
Better physical design tools and tool integration, for instance 3D modeling
 Testing
Different testing schemes
 Capacity
To support high number of gate counts

14.  IP Integration
To support use of commercial IP
 Hard IP Transition
Better physical design tool
 IP Standards
To facilitate use of IP from multiple sources
 IP security
To support various business model

15. SOC INTERCONNECT EVOLUTION
 Early SoCs used an interconnect paradigm inspired by the rackbased
microprocessor systems of earlier days.
 In those rack systems, a backplane of parallel connections formed a ‘bus’ into
which all manner of cards could be plugged.
 A system designer could select cards from a catalogue and simply plug them
into the rack to yield a customized system with the processor, memory and
interfaces required for any given application.
 In a similar way, a designer of an early SoC could select IP blocks, place them
onto the silicon, and connect them together with a standard on-chip bus .
 The backplane might not be apparent as a set of parallel wires on the chip,
but logically the solution is the same.

16. • However, buses do not scale well.
• With the rapid rise in the number of blocks to be connected and the increase in performance demands,
today’s SoCs cannot be built around a single bus. Instead, complex hierarchies of buses are used (as
illustrated in Figure 2), with sophisticated protocols and multiple bridges between them.
• Communication between two remote blocks can go via several buses, and every section of every path
must be carefully verified.
• Timing closure is a growing problem because there is so much that must be checked.

17. • An example of a complex system-on-chip that employs the hierarchical bus solution is the DRACO
DECT-ISDN controller chip (see Figure 3) which was based around the Amulet3i asynchronous
processing subsystem [1].
• This chip incorporates two local processor buses serving the instruction and data requirements of the
Harvard architecture Amulet3 processor core, the asynchronous multi-master MARBLE bus with
production test support [2], and a bridge to a synchronous on-chip bus (SOCB in Figure 4) that serves
the clocked telecommunication peripherals.

18. FUTURE REQUIREMENTS
 The Silistix tools will provide designer-friendly support for selftimed networks-on-chip that
will deliver a robust and cost-effective solution to the requirement for a systematic approach
to on-chip interconnect for complex systems-on-chip. Beyond this, the future presents many
design challenges for on-chip interconnect.
 Quality-of-Service (QoS) support is an obvious next-step, and the feasibility of providing QoS
support on an asynchronous NoC has already been demonstrated [6]. At present the cost of
implementing QoS is high compared with a best-effort network such as CHAIN, where it is
always possible to provide dedicated links for specific connections that require guaranteed
performance.
 The current CHAIN technology assumes that on-chip logic is reliable. It is tolerant to delay
variations, but it is not designed to recover from logic faults or failures. It may become
necessary to design on the basis that on-chip logic is fallible, so that faulttolerance becomes
a requirement for all on-chip functions, including interconnect. Interconnect could be made
fault-tolerant by building redundancy into the fabric, but it is likely to be more cost-effective
(at the low expected error rates) to implement error detection and retry capabilities into the
interfaces, effectively adding faulttolerance as a layer on top of an unreliable fabric (as is the
case with off-chip networks).

19. CONCLUSION:
Packet-switched networks-on-chip are the clear solution to the problem of complex SoC interconnect,
and future developments will see advances in these networks to improve their performance, flexibility,
power-efficiency and functionality. Support for Qualityof- Service protocols, fault-tolerance, secure
communication and other similar high-level functions will emerge over the next few years to establish
the NoC as the de-facto on-chip interconnect technology.