The FPGA design flow document outlines the typical steps for designing an FPGA including: 1) specification and system-level simulation, 2) device selection between Xilinx and Altera, 3) design entry using languages like Verilog and VHDL, 4) functional simulation, 5) synthesis, 6) placement and routing (P&R), 7) timing simulation, and 8) programming and debugging the final design on hardware.

1. FPGA Design Flow
Specification
System-Level Sim
SystemC Model C/C++ Matlab / Simulink
Device Selection
Xilinx Altera
Design Entry Design Entry
Verilog/VHDL Verilog/VHDL/AHDL
CoreGen
LogiBox LPM
IP Schematic FSM Schematic Waveform MegaCore
Function Sim
Cadence Verilog-XL Debussy
Simulation
Model &
TestBench Synopsys VCSi ModelSim
Synthesis Synthesis
FPGA Compiler II LeonardoSpectrum
Synthesis Synthesis
Constraints FPGA Express Synplify FPGA Express FAE Synplify Constraints
P&R Fitting
Placement & Routing Fitting
P&R
Constraints, Fitting
Floorplaning Back Annotate Routing Delay Back Annotate Routing Delay Constraints
Timing Sim
Cadence Verilog-XL Debussy
Timing
Model & Synopsys VCSi ModelSim
TestBench
Prototyping
Third Party Prototyping
Prototyping Development
Programming & Debug Programming & Debug
Hardware Debugger Programmer
SignalTap
JTAG Programmer ChipScope ILA