The document discusses placement and routing in full custom VLSI design. Placement involves techniques like diffusion sharing, gate matrix layout, and common centroid to optimize area and performance. Routing creates physical interconnects and involves global routing, track assignment, detail routing, and search and repair to meet timing constraints while resolving design rule checking violations. The quality of placement impacts routability, and routing aims to minimize delay along critical paths through techniques like buffer insertion and wire sizing.

1. Seminar Placement and Routing options in Full Custom Shankardas Deepti Bharath CGB0911002 VSD528 M. Sc. [Engg.] in VLSI System Design Module Title: Full Custom Physical Design Module Leader: Mr. Chandramohan P.

2. Outline Introduction Full-Custom design methodology Why Is Placement and Routing important? Types of placement techniques in full custom design Routing Routing options Summary

3. Introduction Floor planning CTS Physical Design Partitioning Routing Placement Specification Architectural design Circuit design Physical design Test/Fabrication Logic design

4. Full-Custom Design Methodology Design of a chip from scratch Engineers design some or all of the logic cells, circuits, and the chip layout specifically for a full-custom IC Custom mask layers are created in order to fabricate a full-custom IC Advantages: Complete flexibility, high degree of optimization in performance and area Disadvantages: Large amount of design effort, cost escalation, time to market

5. Why Is Placement and Routing Important? The first phase in the VLSI design that determines the physical layout of a chip. P&R is the first phase in VLSI design that determines the physical layout of a chip Circuit Placement becomes very critical in today’s high performance VLSI design. The quality of the attainable routing is highly determined by the placement. The circuit delay, power dissipation and area are dominated by the interconnections made during routing.

6. For digital custom design Diffusion sharing Gate matrix Transparent latch Folding transistor Tapering For analog custom design Fingering Interdigitization Common centroid Folding technique For mixed signal custom design Shielding power supply and grounding. Types of placement techniques in full custom design

7. (a) Diffusion sharing (b) Gate matrix layout (c) Tapering technique (f) Common centriod (e) Interdigitization (d) Fingering Analog custom design Mixed custom design Digital custom design Placement in Custom Design Figure 1. Placement techniques in custom design

8. After Placement Macros Standard Cells IO Pads Corner Cells VDD rails VSS rails Power & ground straps Figure 2 Chip level placement

9. Routing Routing creates physical connections to a clock and signal pins through metal interconnects Routed paths must meet setup and hold timing and clock skew requirements Metal traces must meet physical DRC requirements Clock nets are routed first followed by signal nets as it’s easier to meet skew and insertion delay targets. Due to the advent of deep sub-micron technology – Interconnect delay constitutes a significant part of the total net delay. – Reduction in feature sizes has resulted in increased wire resistance. – Increased proximity between the devices and interconnections results in increased cross-talk noise. Routers should model the cross-talk noise between adjacent nets. For routing high-performance circuits, techniques adopted: – Buffer insertion – Wire sizing – High-performance topology generation

10. Global Route (GR) GR assigns nets to specific metal layers and global routing cells and avoids congested Gcells while minimizing detours. It gives more accurate parasitic and delay estimates compared to virtual route Global Route Track Assign Detail Route Search & Repair Figure 3 Global Routing Routing options

11. Track Assignment (TA) Assigns each net to a specific track and lays down the actual metal traces It also attempts to: Make long, straight traces and Reduce the number of vias. TA does not check or follow physical DRC rules Global Route Track Assign Detail Route Search & Repair Figure 4 Track Assignment Routing options

12. Detail Routing Detail route attempts to clear DRC violations using a fixed size Sbox. Due to the fixed Sbox size, detail route may not be able to clear all DRC violations. Global Route Track Assign Detail Route Search & Repair Figure 5 Detail Routing Routing options

13. Search & Repair (S&R) Search & repair fixes remaining DRC violations through multiple loops using progressively larger SBox sizes left over from detail route. Remaining DRC violations are addressed by another pass using a larger size SBox. The larger box potentially gives more routing resources to clear violations. Global Route Track Assign Detail Route Search & Repair Routing options Figure 6 Search and Repair

14. After Routing Figure 7 Block level routing Figure 8 Magnified portion of the block

15. Summary Macro and Pad cell locations are defined during the Floorplanning stage, before P&R. Standard cells are placed in “placement rows” during placement. Placement rows are commonly abutted to reduce core area. Cell orientations in abutted rows are normally flipped. Cells in a timing-critical path are placed close together to reduce routing-related delays. The circuit delay, power dissipation and area are the main objective of placement. Rout-ability (or congestion) is a function of the number of available tracks in a given area compared to the number of signals that need to be routed through that area. Routing along the timing-critical path is given priority: Creates shorter, faster connections therby reducing parasitics.

16. References [1] Jon Wateresian (2002) Fabricating Printed Circuit Boards. Massachusetts: Newnes [2] Linfu Xiao, et al. , ‘ Practical Placement and Routing Techniques for Analog Circuit Designs’ , IEEE, Dept. of CSE, Chinese Univ. of Hong Kong, Shatin, China, Dec 2010. [3] Chandramohan P., Digital circuit design and layout, Full custom physical design (VSD 528), session-2 MSRSAS, Bangalore [4] Shawki Areibi and Zhen Yang (2003), ‘Congestion Driven Placement for VLSI Standard Cell, Design’ , School of Engineering, University of Guelph, Ontario, Canada, Dec 2003.

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