FPGA stands for field programmable gate array. FPGAs contain configurable logic blocks that can be connected through connection bars and modified for various applications. FPGAs have different features than ASICs and can be specified using HDL scripts similarly to ASICs. FPGAs provide advantages over ASICs such as shorter design time and lower costs.

1. FPGA
CHAPTER 4
FPGA,CPLD,BIST
The term FPGA stands for field programmable gate array. There are some partially conducting
materials which are referred as configurable logic blocks (CLBs) that are connected through the
connection bars . FPGAs are further modified to various applications that are used to perform
certain operations . There are different features for FPGA from ASICs are used to performance
of various methodologies for a chip testing .FPGA circuits are similar to PLD.FPGA
architecture can be specified with a special script is HDL that as the same properties with
ASIC(Application Specific Integrated Circuits).The structure of ASIC is broadly divided into 3
categories. They are:
 Low level ASIC
 Middle level ASIC
 High level ASIC
The middle level ASIC is divided into two types.They are 1.Gate based ASIC 2.Cell based
ASIC.FPGA provides the better advantages when compared to ASIC.ASIC takes long duration and
it is high cost around thousand dollars to design a chip,where as FPGA are fabricated is short
duration and the cost is about dollars thousand dollars. There are various techniques has been
developed by manufactures when there is need for FPGA for its modules. FPGA has rapid
development in different sectors. FPGA has different domains to implement the various operations.
The low level ASIC has different layouts,procedures and modules that has the various design
fabrication methods in which it is linked to various components to design ASIC. It is called as
schematic procedure.
The High level ASIC has various techniques to design layout in determined way for the
Effective utilization of tools to develop the chip. The important factors of the design aren't
blanketed via way of means of the high-degree descriptions and gear however are taken into
account, in preprocessing.

2. Working of FPGA
FPGAs are programmable integrated chips with a set of programmable blocks surrounded
via way of means of Input or Output blocks which might be prepare via programmable
interconnect resources to become any kind of digital circuit or system .Unlike processors,
FPGAs are honestly parallel in nature.
The structure of FPGA consists of I/O blocks,transfer matrics,CLBs and Interconnects.
FPGAs are programmable silicon chips with a set of programmable common sense blocks
surrounded by Input or Output blocks which might be passes through programmable
interconnect assets to come to be any form of virtual circuit or system.
4.2 Architecture of FPGAs
Figure 5 : Architecture of FPGA
The above figure represents the architecture of FPGA. It consists of Logic blocks,
switchblock, I/O pad, Interconnects. The collection of I/O pads is called as symmetrical
array. The architecture of FPGA is 2-dimensional array blocks in which logic blocks are
connected in between the interconnection matrix. The internal blocks of FPGA are used to
implement about the user logic in order to perform the task.Switch matrix provide the logic
between the two logic blocks. The function of switch block in FPGA as the switch block is a
set of programmable switches that connect fixed routing tracks to other fixed tracks. The
transfer blocks architecture that leads to progressed FPGA density with little impact on the
rate of the FPGA.

3. FPGA logic block
Figure 6 : FPGA logic block
The above figure represents the FPGA logic block. In the above figure the logic block
contains LUT(Look Up Table),D-Flip Flop and Mux.The combination of all the three blocks
is called as CLB(Configurable Logic Block).Here LUT contains four inputs which are
represented as A,B,C,D and the output of LUT is connected to D-Flip Flop and Mux.D - Flip
Flop contains reset pin(Rst) and Clk.The reset pin is used to reset the circuit for every clock
cycle and Clk is used to provide the necessary clocks for the circuits to produce desired
output. LUT implements the combinational logical functions, MUX is used for choice good
judgment, and D turn flop represents the output of the LUT .The simple constructing block of
the FPGA is the Look Up Table. LUTs offer outputs consistent with LUT .
Types of FPGA
Field Programmable Gate Arrays are labeled into three sorts primarily based totally on programs
along with Low-give up FPGAs, Mid-variety FPGAs and high-end FPGAs.

4. 4.5.1 Low-end FPGAs
These are the kind of FPGAs that are designed for only the low electricity consumption,low good
judgment density and complexity of chip. Examples of low stop FPGAs are Cyclone own circle
of relatives from Altera, Spartan own circle of relatives from Xilinx, fusion own circle of relatives
from Microsemi and the Mach XO/ICE40 from Lattice semiconductor
4.5.2 Mid-range FPGAs
These are the form of FPGAs which offer the solution for low-stop FPGAs and high-stop FPGAs.
These are evolved as a stability between the overall performance and the cost. Examples of Mid
variety FPGAs are Aria from Altera, Artix-7/Kintex-7 collection from Xlinix, IGL002 from
Microsemi and ECP3 and ECP5 collection from Lattice semiconductor.
4.5.3 High-end FPGAs
These kinds of FPGAs are advanced for common sense density and excessive performance.
Examples of High-stop FPGAs are a Stratix own circle of relatives from Altera, Virtex own circle of
relatives from Xilinx, Speedster 22i own circle of relatives from Achronix, and ProASIC3 own
circle of relatives from Microsemi.
Configurable logic blocks (CLBs) is a essential constructing block of field-programmable gate
array. As the logic blocks require I/O pads which might be related with connection traces to transmit
the signals. The 3 primary sorts of programmable factors for an FPGA are static RAM,anti-fuses and
flash EPROM.
An FPGA is an organization of good judgment gates which can be hardware programmed carry out
a user-exact task. Programmable good judgment cells interconnected via way of means of a matrix
of wires and programmable switches. Each mobile cellular in an FPGA performs a good judgment
function.Configurable good judgment block or good judgment blocks is a essential constructing
block of subject programmable gate array(FPGA). Logic blocks require I/O pads and routing
channels.These I/O pads are used to interface with outside alerts and routing channels are used to
interconnect with good judgment blocks.
FPGAs are programmable silicon chips with the collection of Programmable good judgment blocks
surrounded via way of means of I/O blocks which can be placed together Programmable
interconnection.

5. The FPGA is an integrated circuit that contains millions of logic gates in which they are
connected together by switches in order to perform certain task. In FPGA basically there are
two memory blocks.There are Random Access Memory(temporary memory) and Read Only
Memory(permanent memory).The data of permanent memory is written as part of FPGA
configuration and that cannot be modified.The configurable logic blocks are the basic logic
units of an FPGA.It is referred as logic blocks.CLBs are designed with major components D-
Flip Flop and LUTs.The design of FPGA are mainly coded mainly using hardware
description language(HDL) such as Verilog and VHDL.The output file that contains inter
connect description is usually called called as bitstream,which is programmed to FPGA.
4.3 Characteristics of FPGA
1.FPGA design ASIC ,the user does not produce any cheap production ,user can get
combination of chips.
2.FPGA can do all semi-custom ASIC circuit of sample.
3.FPGA has which inter trigger and I/O pin.
4.4 Advantages of FPGA
1.It has longer duration period.
2. Short duration availability exchange place .
3. Past and high performance system.
4.Speed of software is high.
5.Real time applications.
4.5 Disadvantages of FPGA
1. The programming is not as simple as c programming.
2. Engine is need to have knowledge of about usage of simulation tools to design.
3.Power consumption is more.

6. 4.6 Applications of FPGA
Figure 7 : Applications of FPGA
1.Consumer Electronics
The purchaser electronics enterprise is ready to be fast to marketplace with new merchandise in
flat panel displays, transportable media players, and domestic networking merchandise.
2.Security Systems
With the wi-fi communications generation in records protection development, it will increase
the necessities for protection and confidentiality, the use of the safety control approach and
protection generation faces new challenges. The use of converting into secret code by wi-fi
conversation has come to be the bottleneck of steady conversation system.
3.Video and Image Processing
FPGAs are an excellent match for video and picture processing applications, which include
broadcast infrastructure, clinical imaging, HD videoconferencing, video surveillance, and
military imaging, wherein there may be a want to have a scalable answer for enhancing cost,
performance, flexibility and productiveness requirements.

7. 4.Aerospace and Defense
FPGA traits in aerospace and defense packages contain security, tools, and specialization. FPGA's
constitute one sort of programmable virtual processor with many gates that allow systems
designers to custom-application the tool at the fly for security, functionality, electricity
consumption, and other benefits.
5.Wireless Communication
Making Calls. On a worldwide level, billions of human beings have subscriptions for mobile
communication. Connecting Devices. Bluetooth era lets in human beings to attach numerous
devices.
6.Medical Electronics
Medical digital gadgets cowl a spectrum of equipment implementations, starting from massive
diagnostic imaging machines that fill a room, to small cellular gadgets that sufferers deliver with
them. Driven via way of means of healthcare dynamics for advanced affected person care at
decrease costs, companies are traumatic accelerated visualization and transmission of clinical
picture and video facts from sufferers facts.
7.Scientific Instruments
FPGAs provide wide range of applications in scientific instruments in order to verify each
and every component in the proper way to test a chip.
8.Distributed Monetary Systems
Distributed Monetary Systems of FPGA consists of virtual sign processing, bioinformatics, tool
controllers,software-described radio, random logic, ASIC prototyping, clinical imaging, laptop
hardware emulation, integrating a couple of SPLDs, voice recognition, cryptography, filtering and
communication encoding.

8. CPLD
The acronym of CPLD is Complex Programmable Logic Devices. Programmable logic
device or PLD (SPLD) can handle 10-20 logic equations. For more complex Circuit complex
PLD (CPLD) can be used in PLDs are interconnected. Two level of programming is used one
for PLD and another for switches in interconnection block. Transistors are used as switches.
I/O, O/P are routed through I/O block which provides buffering. The below figure describes
about structure of CPLD.
CPLD consists of I/O blocks, PLDs and Interconnection matrix. Interconnection matrix
connects PLDs on both sides and further it is connected to I/O blocks on both the sides. A
complex programmable logic device (CPLD) is a common sense tool with completely and
outputs are linked collectively through a international interconnection matrix. CPLD has
degree of programmability: every PLD block may be programmed, after which the inter
connection among the PLD’S may be programmed. CPLD is applicable for manipulate circuit
due to the fact they've more combinational circuits. CPLD may be used to low –give up
merchandise while FPGA is used for high-give up merchandise. CPLD has much less as
compared to FPGA concerning design complexity. CPLD has much less operational speed.
CPLD gadgets aren't volatile. These include flash or erasable ROM reminiscence in all of the
cases. CPLD is a ROM base.
Figure 8 : Block diagram of CPLD
In Complex Programmable Logic Device, AND gate and OR gate are programmable.Above
figure represents group of PLDs which are connected in between the I/O blocks through
Interconnection matrix. CPLD is used to control the combinational circuits.CPLD is used for
low-end products and FPGA is used for high-end products. Number of components are
required to fabricate in CPLD is less when compared to FPGA.As CPLD

9. requires less number of logic gates to design,as it is a low-end product.CPLD has ROM (i.e
permanent)memory.CPLD has large number of blocks and also it contains flip flops. CPLD
could work immediately 6after power-up. CPLD has high speed than FPGA due to its design.
CPLD is non-volatile memory. CPLD based on EPROM or EEROM technology.
4.7 Comparison between CPLD and FPGA
Figure 9 : Comparison between CPLD and FPGA

10. Some of the applications of CPLD are as follows:
1.Cost sensitive.
2. Usage of Low power.
3.Battery operated portable devices due to its low size.
4.1.2 BIST
The acronym of BIST is Built-in-self test.It is a technique which is used self test the
integrated chip that has inbuilt hardware and software. The aim of BIST technique is to avoid
costly use of ATE( Automated Test Equipment ) testing.As IC’s are getting complex,many
blocks are integrated in IC with analog and digital ports,inthat ATE testing is difficult and
costly service.It is also useful to blocks of IC which has no direct connection with external
pins. As IC’s are upgrading in future conventional testers will no longer be adequate for the
latest and fastest chip.
4.8 Types of BIST
Basically there are different types of BIST but most commonly used BIST are Logical BIST
and Memory BIST.
4.13.1 Logical BIST(LBIST)
Logic is used to test under this technique. The quasi spot sequence generator is to generate
random input pattern. MISR determines the input and the output pattern of the method.
Memory BIST(MBIST)
It is used for testing memories. There are some standard industrial test patterns that are used
to apply, read and compare test patterns.The industry standard MBIST are
1. By March model
2. By spotted model
3. The various design model.

11. 4.9 Architecture of BIST
Figure 10.Architecture of BIST
The above figure represents the Architecture of BIST.In this architecture there is input which is
used for self-test through the test controller. The test controller gives the signal to the Hardware
pattern generator, it may be a pseudo random generator which generates the random code. The
random code generator combines with the normal input which is provided to MUX, as the
selection lines for MUX is taken from the test controller as shown in above figure.As test
controller provides enable signal of testing by which hardware pattern generator is selected at
the out of the mux. When the test controller provides disable signal for testing by which normal
input is selected and it is generating at the output of MUX. The output of the MUX is given to
Circuit Under Test (CUT), based on signal enable or disable signal is given to CUT. When the
Test Controller provides the enable signal to the CUT is provides different test patterns at the
output based on the input. Based on data pattern ,one can identity the output is fault or not.
There will be different test patterns at the output based on the input combinations.As there is a
various test pattern to minimize the complexity output response compactor. The output response
of compactor has MBIST. The output response compactor provides the signature output.It
provides fractional portion of faulty outputs, if it provides all the faulty patterns at the output
the testing time period of output response of compactor will increase.The output of test

12. controller is given to ROM (Read Only Memory) which as the reference signature.The output
response compactor signature output and the reference signature is given to the compartor.The
comparator identifies the test pattern are either good or faulty test patterns
Issues of BIST designing
1. how many faults to be covered.
2. how much chip area occupied by BIST.
3.Test time
4.Flexibility by software and hardware
4.10 Advantages
1.It lowers the testing cost.
2.Testing is independent on future technology.
4.1 Disadvantages
1.Additional circuit(silicon area)for BIST testing in IC.
2.Additional pin required for BIST testing in IC.
3.On chip testing may get failed then how to test it.
4.2 Applications
BIST(Built in self test) is commonly placed in military industries,Biological activities,self
starting applications,blocks design,large development blocks.
4.3 Realization of Logic Gates
In Verilog HDL a hardware design can be described in four different styles (levels). They are,
1.Circuit level (or) switch level
2.Fundamental level
3.Data flow level
4. Behavioral level.

13. 4.14.1 Gate Level or Structural Level
The higher level of design description next to circuit level is the fundamental level. In this
structure, a digital circuit is described in terms of various building blocks like and, or, nand,
nor, XOR and XNOR. All the basic gates are available as ‘primitives’ in Verilog. Primitives
are general modules that are predefined in Verilog. They can be incorporated (instantiated)
directly in other modules. More complex circuits can be modeled by repeated and successive
instantiation of the ‘primitives’.