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![Slide 17
Hierarchical view of Energy Conservation
Software
Definitions
Dynamic system monitoring and intelligent control of energy
savings, work load profiling, [dvfs], profiling and partitioning
Architectural
Definitions
Heterogeneous processing resource optimization: MCU, DSP,
accelerators, functional processing units, memory usage
optimization
Design
Definitions
Hardware support for voltage islands, power gating, low-
power idle modes, SRPG, AWB, DVFS, DPTC, clock gating
PROCESS node
Definitions
Transistor design, Vt Optimization, memory bitcell design.
Special circuits, libraries, custom and analog blocks, SOI
Power Trees/Voltage islands, Connectivity of components & consistent
platform power modes, intelligent bus coding, dependency
discovery/optimization
Platform
Definitions
Thanks to Milind Padhye, Freescale Semiconductor, Austin Wireless Design Center](https://image.slidesharecdn.com/schulzaustinq22008-130422130434-phpapp01/85/Low-Power-Design-and-Verification-14-320.jpg)
![– 11 –Innovation Through Collaboration – 11 –Innovation Through Collaboration – Low Power Coalition
CPF Language
● CPF is TCL-based.
● CPF Language = TCL commands + CPF objects + Design objects
Power domain
Analysis view
Delay corner
Library set
Operating condition
● Design objects: objects that already exist in the RTL/gate netlist
Module, Instance, Net, Pin, Port
● Commands – 42 commands
set_* commands [version, scope, and general commands]
define_*_cell commands [library cell description]
create_*_rule commands [design intent]
update_*_rules commands [implementation directives]](https://image.slidesharecdn.com/schulzaustinq22008-130422130434-phpapp01/85/Low-Power-Design-and-Verification-32-320.jpg)
![– 24 –Innovation Through Collaboration – 24 –Innovation Through Collaboration – Low Power Coalition
Specify Power Mode Transitions
create_mode_transition -name PM1toPM2 –from_mode PM1 –to_mode PM2
-start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } –cycles 100
create_mode_transition -name PM2toPM3 –from_mode PM2 –to_mode PM3
-start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } –cycles 1000
create_mode_transition -name PM3toPM4 –from_mode PM2 –to_mode PM3
-start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } –cycles 1000
create_mode_transition -name PM4toPM1 –from_mode PM2 –to_mode PM3
-start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }
-clock_pin { pcu_inst/clk } –cycles 200
PDcore PDau PDlu PDalu PDrf
PM1 1.2v
0.8v
PM3 0.8v off off off 1.2
PM4 0.8v 1.2v 1.2v 1.2v off
1.2v 1.2v 1.2v
PM2
1.2v
1.2v 1.2v 1.2voff
PM1
PM2
PM3
PM4](https://image.slidesharecdn.com/schulzaustinq22008-130422130434-phpapp01/85/Low-Power-Design-and-Verification-34-320.jpg)
![Silicon Integration Initiative 6
set_design top
# Set up logic structure for all power domains
set_time_unit us
set_power_unit uW
create_power_domain -name PDcore -default
create_power_domain -name PDalu -instances {inst_A inst_B} -shutoff_condition {!pm_inst.pse_enable[0]}
create_power_domain -name PDrf -instances inst_C -shutoff_condition {!pm_inst.pse_enable[1]}
create_power_domain -name PD4 -instances inst_D -shutoff_condition {!pm_inst.pse_enable[2]}
# Define static behavior of all power domains and specify timing constraints
create_nominal_condition -name high -voltage 1.2
create_nominal_condition -name medium -voltage 1.1
create_nominal_condition -name low -voltage 1.0
create_power_mode -name PMhot -domain_conditions {PDcore@high PDalu@medium PDrf@high PD4@low} -default
create_power_mode -name PMcool -domain_conditions {PDcore@high PDrf@high PD4@low}
create_power_mode -name PMsleep -domain_conditions {PDcore@high PD4@low}
create_power_mode -name PMhibernate -domain_conditions {PDcore@low}
# Set up required isolation and state retention rules for all domains
create_state_retention_rule -name sr1 -domain PDalu -restore_edge {!pm_inst.pge_enable[0]}
create_state_retention_rule -name sr2 -domain PDrf -restore_edge {!pm_inst.pge_enable[1]}
create_state_retention_rule -name sr3 -domain PD4 -restore_edge {!pm_inst.pge_enable[2]}
create_isolation_rule -name ir1 -from PDalu -isolation_condition {pm_inst.ice_enable[0]} -isolation_output high
create_isolation_rule -name ir2 -from PDrf -isolation_condition {pm_inst.ice_enable[1]} -isolation_output high
create_isolation_rule -name ir3 -from PD4 -isolation_condition {pm_inst.ice_enable[2]} -isolation_output low
create_level_shifter_rule -name lsr1 -to {PDcore PDrf}
end_design
CPF Format Concepts
Define
PDs
Define
Nominals
PMs
Bind PD & NC
Rulesand
morerules
What if this command was in a different file and
the IP in PDcore had not been characterized at
the “low” nominal condition?](https://image.slidesharecdn.com/schulzaustinq22008-130422130434-phpapp01/85/Low-Power-Design-and-Verification-72-320.jpg)
![Silicon Integration Initiative 7
CPF Relational Analyzer
• Each object in the CPF hierarchy is tracked separately via metadata
• Architecture handles hierarchy merging, module cloning & port mapping
• Broad analysis – Analyze all objects and all O2O relationships
• Deep analysis – Every attribute, every object with every update
Interactive and Incremental:
Designed for “Hands-on” learners with English as a Second Language
Exposes the final state of the design intent compiled from many sources
Search and Report capabilities:
All searches can use standard wildcards of *, ?, [a-z], [0-9]
Any combination of CPF Objects, Property Names and Property Values](https://image.slidesharecdn.com/schulzaustinq22008-130422130434-phpapp01/85/Low-Power-Design-and-Verification-73-320.jpg)
More Related Content
Similar to Low-Power Design and Verification
Low-Power Design and Verification
- 1. Si2 - InnovationThrough Collaboration Steven E. Schulz President and CEO May 20th , 2008 DVclub – Austin, TX Low-Power Design and Verification
- 2. 2Si2 – InnovationThrough Collaboration Today’s Agenda
- 3. 3Si2 – InnovationThrough Collaboration Today’s Agenda • Why Low-Power Now? • Design and Verification Flow Challenges / Reqts • Common Power Format Introduction / Examples • Industry / Market Adoption and Silicon Benefits • Introduction to the Low Power Coalition • 2008 Roadmap / Plans • Q & A
- 4. Page 3 HereWeare 2001 InternationalTechnology Roadmap for Semiconductors P = ACV2f + VIleak Junction Leakage Possible kink in dynamic power Dynamic power Sub- threshold Gate Junction
- 5. Page 2 Power Motivationand Requirements Mobile applications trends: • Leakage is significantly increasing due to process scaling • Active power increases due to application integration (with the subsequent exponential increase in leakage). Current density is also on the increase. • Active leakage is now a significant portion of SoC active power budget. • Sleep mode techniques need to be enhanced and enabled in a consistent fashion throughout the design flow • We need a concerted effort applied to leakage minimization at the micro- architectural, system and software level. • Process variation now limits how much we can voltage scale and how we do our power accounting, and therefore new strategies need to be develop to capture these constraints, and enhance our current scaling approaches/methodologies.
- 6. © 2006 VirageLogic Corporation – COMPANY CONFIDENTIALSlide 18 Ultra-Low-Power Applications Addressing a Wide Range of Requirements Ultra-Low-Power Applications Addressing a Wide Range of Requirements
- 7. Excel Your Ideato Silicon 10 PowerSmart™ -- Low Power Design Methodology Power switch1.5V OP buffer 1.5V OP D Q ck Vdd_UPSVdd Retention flip-flop Isolation cell Power Islands Multi-Vt library Multi-Vth (Fusion) clk en o Integrated clock gated cell Clock Gating Level shifter Level shifter Multi-output regulator Regulator 1.2V 1.0V 0.8V 3.3V Multi-VDD Multi-VDD library 1.2V1.0V 0.8V Low power IP SRAM Low Power IP
- 8. October 5, 20063 Processordesign for Power Efficiency: Different needs for different markets • Server market: – Defining property: Server processors are rarely idle. – Power goal: Increase MIPS/Watt in Power State C0 (ACPI). • Mobile market: – Defining property: Laptop processors are mostly idle. – Power goal: Reduce power in C2/C3 power states. • Techniques: – Clock gating – Multiple power domains – Multiple threshold voltages – Headers/footers – Operand Isolation (holding cell inputs stable when output is unused) – Dynamic voltage and frequency scaling – And others…
- 9. October 5, 20064 Poweranalysis challenges: More complex than timing analysis • It is pattern-dependent. – Circuit and gate-level power analysis require good RTL-level patterns for accurate results. • It is a balancing act. (power efficiency) – Performance per watt (efficiency) is the metric, not Watts. Need to find blocks or nets that consume power without appropriate performance benefit. – Many tools sort blocks and nets by total power consumption not performance/watt. (E.g. clock nets burn a lot of power, but we already knew that) • It is an aggregate (time and space) and a user-defined constraint. – Power analysis types: average power (for budgeting & package selection), energy (for battery life), peak power (IR drop analysis), etc. – E.g. Briefly higher localized power consumption can be tolerated for package selection, unless it exceeds limits. • It requires coordination of data from physical design, gate design, RTL, and verification domains. – It requires knowledge in all these domains to cross-check results. • Must allow for accuracy to be improved over time. – Detailed circuit-level power analysis data often comes too late in the design cycle.
- 10. October 5, 200611 Otherrelated issues: DFT and Timing • Are scan paths hooked up in the RTL? Are they simulated in the Verilog? How are they verified? • How do you analyze power consumption in scan mode? • Timing also needs to know about the multiple voltage domains and operating points. • Need to work on timing and power in one environment to achieve correct optimization and trade-offs.
- 11. Slide 8 System Aspectsrequire differing views Layout Algorithm Bus Architecture Implementation Power Source Temperature Refinement Security Address Space Documentation
- 12. Slide 9 Address space Layout Algorithm BusArchitecture Implementation Power Source Temperature Refinement Security Address Space Documentation
- 13. Slide 10 Aspect View:Bus Architectural layout CPUCPUCPU FLASHFLASH USBUSB UARTUART GPIOGPIO PLLPLL Peripheral Bus Processor Bus BridgeBridge SRAMSRAM EthernetEthernet…… DMADMA DMADMA Layout Algorithm Bus Architecture Implementation Power Source Temperature Refinement Security Address Space Documentation
- 14. Slide 17 Hierarchical viewof Energy Conservation Software Definitions Dynamic system monitoring and intelligent control of energy savings, work load profiling, [dvfs], profiling and partitioning Architectural Definitions Heterogeneous processing resource optimization: MCU, DSP, accelerators, functional processing units, memory usage optimization Design Definitions Hardware support for voltage islands, power gating, low- power idle modes, SRPG, AWB, DVFS, DPTC, clock gating PROCESS node Definitions Transistor design, Vt Optimization, memory bitcell design. Special circuits, libraries, custom and analog blocks, SOI Power Trees/Voltage islands, Connectivity of components & consistent platform power modes, intelligent bus coding, dependency discovery/optimization Platform Definitions Thanks to Milind Padhye, Freescale Semiconductor, Austin Wireless Design Center
- 15. Slide 18 Low PowerDesign Needs Support Low Power Design Techniques thru the entire design flow using a single file format. Design Representation – Accurately define and capture the low power design intent, modes and constraints. Design Implementation – Floorplan and power grids. – Common constraints for all tools (Synthesis, APR, timing, DFT) – Design analysis tools with single power constraints. – Accurate power estimation and measurements Design Verification – Voltage oriented simulators – Various static power technique modeling and simulations. – Silicon validation and correlation.
- 16. Page 5 The verificationflows need to enable: • a voltage aware simulation method for logic problems due to voltage island partitioning • a method for full design multi-voltage domain analysis and reporting • a vector-less rule driven analysis of architecture, RTL, and gate correctness • a method for equivalence checking (i.e. across voltage states ) • a method that captures Island ordering • a method that incorporates early detection of micro-architecture sequence errors Flow and Methodology Requirements
- 17. Si2-Accelera Low PowerWorkshop, CTO/SoCDT, Herve Menager, October 5th, 2006 3 Low power implementation : What’s new ? Becoming mainstream: – For 65nm and below , Low power is crucial for low/high performance. So far: – For dynamic power • Reducing power dissipation source when not needed. • Minimize switching capacitances. – For static power • Use of multiple Vt(s) synthesis / optimization More recently: – Reducing supply reduces power, but also makes circuit slower. To meet both chip performance requirements and power goals, use voltage islands and voltage and frequency scaling. – Leakage can also be addressed by suppressing current when not needed. Island of voltages increases the difficulty on implementation techniques. Intrusive on functionality Impact across design tasks ( Design-In and Implementation )
- 18. Si2-Accelera Low PowerWorkshop, CTO/SoCDT, Herve Menager, October 5th, 2006 4 Design implementation challenges New cells and their use model – Level Shifters – Retention logic – Isolation logic – Micro Switches Impacts at all levels of the design flow – Interface logic design, partitioning – Verification of power modes – Checks on interfaces between Power domains – Placement of IP in context voltage islands – Floorplanning with switches, Irdrop across switches, transient behavior. – DFT – Verification (STA, LVS, analysis) Conceptual shift : Power nets become functional signals
- 19. Si2-Accelera Low PowerWorkshop, CTO/SoCDT, Herve Menager, October 5th, 2006 6 Methodology and design flow impacted
- 20. Si2-Accelera Low PowerWorkshop, CTO/SoCDT, Herve Menager, October 5th, 2006 10 Short Term need ( 2) – Fill hole in Verification Low leakage design techniques have created a real paradigm shift. Power and ground nets are now becoming functional nets. They are not all explicitly in RTL or netlist levels. Proper connection of any other functional nets is verified by functional simulation….against the RTL or netlist. Being able to verify the power down modes , retention, recovery at power-on, etc in the context of RTL simulation is becoming mandatory. Verification tools should be power modes aware.
- 21. 6 For IP, contextis key Memory Processor SoC “Always-on” depends on context Buffer within CPU SoC buffer routed across CPU Characterization range is important Cells, memory could be different Complex features Multiple VDD, VSS pins Multiple operating voltages Voltage dependent behavior Closed-loop behavior (tunable voltage) Don’t want formats limiting IP features
- 22. 2 Canonical design toargue over……. Start with a realistic example to exercise interfaces and control Power and Ground are signals – but not as we know them…….. Power Gating, Retention, (Dynamic) Voltage Scaling, Level shifters, Memory… Isolation clamps across boundaries, a number of supply voltages e.g. a SOC with always powered logic plus: VSOC RAM with Core Retention (& additional power rail?) VRAM PG sub- system RETAIN SRPG subsystem RETAIN CPU DVFS (& LV retention?) VCPU
- 23. 14 Addressing power managementchallenges Operational and Standby (leakage) Active power + leakage Power gating/voltage scaling On-chip – fast but with care to avoid dI/dt problems Off-chip – may add latencies as long as 100’s of microseconds Need to be able to quantify Real-time cost (e.g. interrupt latency) in “wake-up” times Energy cost functions getting into/returning from power saving states
- 24. 4 © NOKIAUPF Workshop / Oct 2006 /Naula Current state … • Debugging capabilities are very poor • Capacity issues • Complexity issues • Reporting weak and misleading • Functional correctness difficult to verify • Tools are mostly in Gatelevel, should be in RTL • Important is to have accuracy for RTL or otherwise it is not useful • All tools using different description for PM • PM configurations currently having thousands of statements in SoC level • No automation; It is designers responsibility to verify that all definitions are done correctly • Because updates for these definitions are done quite seldom, it is difficult to keep in mind complex configurations • There is no automation for PM definitions verification • Design hierarchy presentation varies in configuration files between tools, also between RTL and gate in same tool. Syntax is effected by scripting languages like perl and tcl
- 25. © 2006 VirageLogic Corporation – COMPANY CONFIDENTIALSlide 7 Traditional Design FlowTraditional Design Flow HW/SW Co- Design Architecture Design RTL Design Placement & Optimization Floorplanning Synthesis Clock Synthesis Optimization Routing & Optimization Sign-off: DRC/LVS Timing Verification Logic Verification
- 26. © 2006 VirageLogic Corporation – COMPANY CONFIDENTIALSlide 9 Techniques Relevant To IPTechniques Relevant To IP Right size libraries – Smaller transistors lead to smaller parasitics – Performance trade-off Multi-Vt libraries – Right Vt for the right paths at the right performance – Effectively used to control leakage – Increases the number of libraries needed to implement the design Voltage Islands – Requires updates to deal with multiple power supplies and associated conditions – Requires special level shifting components to implement Power Gating/On-Chip Regulation – Requires special power gating cells/regulation cells – Need to deal with “derived” power nets – Need to deal with POR cycle Substrate Bias – Requires dealing with multiple power supplies and possibly “negative” power supplies – Requires special level shifting components to implement
- 27. © 2006 VirageLogic Corporation – COMPANY CONFIDENTIALSlide 10 So What Changes? … Everything …So What Changes? … Everything … Low Power Core Voltage Island Support Voltage Island & State Retention Support On Chip Regulation Support Voltage Island & Back Bias Support VDD VSS VDD1 VSS VDD2 VDD VSS1 VSS VSS VDD
- 28. © 2006 VirageLogic Corporation – COMPANY CONFIDENTIALSlide 12 So What Changes? … Everything …So What Changes? … Everything … HW/SW Co- Design Architecture Design RTL Design Placement & Optimization Floorplanning Synthesis Clock Synthesis Optimization Routing & Optimization Sign-off: DRC/LVS Timing Verification Logic Verification Power Sign-off Spec
- 29. – 4 –InnovationThrough Collaboration – 4 –Innovation Through Collaboration – Low Power Coalition LibrariesIP What Was the Problem? Logic Information (Verilog) Synthesis Test SVP Formal Analysis Simulation ParserParser Parser Logic is “Connected” P+R Parser Parser Parser Can be Automated Hardware Parser Equivalence Checking Parser Management Parser Power Information (CPF) Power is Not “Connected” Very Difficult to Automate Power Information (no consistency) LibrariesIP Synthesis Test SVP Formal Analysis Simulation ParserParser Parser P+R Parser Parser Parser Hardware Parser Equivalence Checking Parser Management Parser
- 30. – 8 –InnovationThrough Collaboration – 8 –Innovation Through Collaboration – Low Power Coalition ● Dec 4, 2006 Cadence contributed CPF v1.0 to Si2 ● January 12, 2007 LPC members unanimously voted and approved CPF v1.0 as Si2 Specification for low power standard ● January 17, 2007 Cadence contributed CPF v1.0 parser source code to Si2 ● March 5, 2007 CPF 1.0 available to everyone at no cost as a Si2 standard Si2 CPF Standardization
- 31. – 10 –InnovationThrough Collaboration – 10 –Innovation Through Collaboration – Low Power Coalition Common Power File ASCII file to capture ● Design intent and constraints Power domain Logical: instances as domain members Physical: power/ground nets and connectivity Analysis view: timing library sets for power domains Power Logic Level Shifter Logic Isolation Logic State-Retention logic Switch Logic & Control Signals Power mode Mode definitions Mode transition definitions ● Technology information Level Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells, Always On Cells
- 32. – 11 –InnovationThrough Collaboration – 11 –Innovation Through Collaboration – Low Power Coalition CPF Language ● CPF is TCL-based. ● CPF Language = TCL commands + CPF objects + Design objects Power domain Analysis view Delay corner Library set Operating condition ● Design objects: objects that already exist in the RTL/gate netlist Module, Instance, Net, Pin, Port ● Commands – 42 commands set_* commands [version, scope, and general commands] define_*_cell commands [library cell description] create_*_rule commands [design intent] update_*_rules commands [implementation directives]
- 33. – 12 –InnovationThrough Collaboration – 12 –Innovation Through Collaboration – Low Power Coalition Minimal Command Set For Different Design Stages create_power_domain create_nominal_condition create_power_mode create_state_retention_rule create_isolation_rule create_level_shifter_rule define_library_set update_nominal_condition update_power_mode create_ground_nets create_power_nets update_power_domain create_power_switch_rule create_analysis_view create_operating_corner Specify power intents verification and simulation design exploration early power estimation More implementation details synthesis formal verification DFT, ATPG, gate level power estimation Complete physical implementation details silicon virtual prototyping power planning physical synthesis structural verification sign-off power analysis
- 34. – 24 –InnovationThrough Collaboration – 24 –Innovation Through Collaboration – Low Power Coalition Specify Power Mode Transitions create_mode_transition -name PM1toPM2 –from_mode PM1 –to_mode PM2 -start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] } -clock_pin { pcu_inst/clk } –cycles 100 create_mode_transition -name PM2toPM3 –from_mode PM2 –to_mode PM3 -start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] } -clock_pin { pcu_inst/clk } –cycles 1000 create_mode_transition -name PM3toPM4 –from_mode PM2 –to_mode PM3 -start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] } -clock_pin { pcu_inst/clk } –cycles 1000 create_mode_transition -name PM4toPM1 –from_mode PM2 –to_mode PM3 -start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] } -clock_pin { pcu_inst/clk } –cycles 200 PDcore PDau PDlu PDalu PDrf PM1 1.2v 0.8v PM3 0.8v off off off 1.2 PM4 0.8v 1.2v 1.2v 1.2v off 1.2v 1.2v 1.2v PM2 1.2v 1.2v 1.2v 1.2voff PM1 PM2 PM3 PM4
- 35. – 27 –InnovationThrough Collaboration – 27 –Innovation Through Collaboration – Low Power Coalition Low Power Design Verification Using CPF ● No need to specify power or ground nets at RTL stage ● No need to specify implementation related constraints at this stage such as library, timing constraints etc ● Minimal set of CPF commands for front-end designers to use Simulation tools to simulation power domain on and off to simulate power mode transitions for DVFS Coverage tools to check power mode coverage to check power mode transition coverage Assertion tools to generate power domain and mode aware assertions Verification tools to check for the correctness and completeness of CPF
- 36. – 33 –InnovationThrough Collaboration – 33 –Innovation Through Collaboration – Low Power Coalition Low Power Logic Implementation and Verification Using CPF ● Still, no need to specify power or ground nets at this design stage ● Minimal set of CPF commands for designers to use Logic synthesis tools to synthesize isolation, level shifter and state retention logic to perform power domain aware logic synthesis to perform power mode aware (DVFS) synthesis Test synthesis tools to perform power domain and power mode aware DFT synthesis to generate power domain aware test control logic Formal Verification tools to check the correctness of low power structural implemented by synthesis tools to perform low power equivalency checking (RTL+CPF vs Netlist) Simulation tools to perform power aware gate level simulation to generate additional assertions for gate level simulation Analysis tools to perform power domain aware and power mode aware power analysis
- 37. – 45 –InnovationThrough Collaboration – 45 –Innovation Through Collaboration – Low Power Coalition ? CPF Enabled Low Power Design Flow Design Creation b Synthesis Constraint Generation Design for Test SVP EquivalenceChecking ConstraintValidation Specification Function, timing, power RTL Coding RTL + CPF Coding Iterate Quick architectural explorationRe-use pre- verified IPInstantiate single RTL with different power profiles Hand off to drive physical implementation Physical Implementation Chip Integration Prototyping Physical Synthesis Routing DFT Analysis Sign-off ATPG ConstraintValidation Equivalence checkingLVS/DRC/Ext GDSII Constraints CPF Netlist Golden specification eliminates assumptions and miscommunications Automatic partitioning of power domains Automatic scheduling of test modes Single power specification used from specification to GDSII VerificationCoverage TestbenchAutomation Verification Structural & Funct. Checks Formal Analysis Simulation Acceleration & Emulation Functionally verify advanced power implementation techniques Iterate
- 38. Power Forward InitiativeContinues Growth 24 companies across the design chain www.powerforward.org 26
- 39. – 48 –InnovationThrough Collaboration – 48 –Innovation Through Collaboration – Low Power Coalition 48 TSMC 8.0 Low Power Reference Flow CPFCPF CPF Quality Check Conformal Low Power CPF Quality Check Conformal Low Power CPF-Enabled Functional simulation Incisive Design Team Simulator Incisive Design Team Manager CPF-Enabled Functional simulation Incisive Design Team Simulator Incisive Design Team Manager CPF-Enabled Logic Synthesis & DFT Encounter RTL Compiler CPF-Enabled Logic Synthesis & DFT Encounter RTL Compiler CPF-Enabled LEC + Power Checks Conformal Low Power CPF-Enabled LEC + Power Checks Conformal Low Power CPF-Enabled LEC + Power Checks Conformal Low Power CPF-Enabled LEC + Power Checks Conformal Low Power CPF-Enabled Timing & SI signoff Encounter Timing System CPF-Enabled Timing & SI signoff Encounter Timing System CPF-Enabled Physical implementation SoC Encounter CPF-Enabled Physical implementation SoC Encounter CPF-Enabled Logic simulation Incisive Design Team Simulator CPF-Enabled Logic simulation Incisive Design Team Simulator CPF-Enabled ATPG Encounter Test CPF-Enabled ATPG Encounter Test CPF-Enabled IR drop & Power signoff VoltageStorm-DG CPF-Enabled IR drop & Power signoff VoltageStorm-DG CPF-Enabled Leakage & Thermal Analysis Encounter Timing System CPF-Enabled Leakage & Thermal Analysis Encounter Timing System www.tsmc.com
- 40. Confidential ARM1176-IEM iRM Features AutomatedRTL to GDS Multi Supply Voltage Implementation flow CPF based flow CPF file is used to describe the low power intent and to drive implementation and verification flow Multi Mode Multi Corner (MMMC) analysis and optimization Ensures design is optimized across complete voltage and frequency range Tri-lib based flow Provides accurate interpolation for DVFS and IR drop analysis ECSM extensions to .lib
- 41. Confidential CPF Flow Availability VRAM VDDCO REVDDRA M VSS VRAM VCORE VSOC ARM1176-IEM iRM available now from ARM Shipped along with standard ARM1176 RTL deliverables Includes CPF, scripts, documentation and front end libraries (130G) Port to ARM Advantage 65GP in H108
- 42. – 49 –InnovationThrough Collaboration – 49 –Innovation Through Collaboration – Low Power Coalition 49 ARC Proof Point Project Using CPF Based Low Power Solution ● Simulation with CPF identifies problems that you will not otherwise identify ● CPF aids communication of power intent across team boundaries, ensuring accurate implementation at all flow stages ● Significant power savings results using these techniques Always On SCQSCQSCQ SCQ SCM SDMSIMD SCM SDM I$ D$ SCQARC700 I$ D$ Clock Gating Domains Power DomainsFunctional Blocks ARC700 with SIMD Co-Processor • For high bit-rate data streams, both the ARC and the SIMD run flat out • For lower bit-rate data stream, the subsystem can be run at a lower frequency • For generic processing, the SIMD can be inactive Power Forward low-power implementation & verification project results
- 43. Copyright© 2007. ARCInternational. All rights reserved. • ARC Energy PRO: new active power management technology – Reduces power by as much as four fold – End-to-end fully verified power management solution – reduces TTM – Ideal for battery-operated portable applications • Integrated with Cadence Low-Power Solution and CPF to ensure accurate implementation at all flow stages • Energy PRO technology will be included in future ARC processor cores and multimedia subsystems
- 44. 51 ©2008SequenceDesign,Inc. CPF Out CurrentStatus and Next Steps Released to customers on Feb 11th, 2008 An official part of the PowerTheater 2008.1 release CPF Out marked as beta in the release Tested the flow using RC on numerous small tests and the Nano CPU example from Cadence Next Steps Get feedback from key customers over the next month Verify interpretation of create_global_connection, create_power_nets and create_power_switch commands Do a CPF-In for power verification flow Leadership in Design for Power (DFP)
- 45. – 51 –InnovationThrough Collaboration – 51 –Innovation Through Collaboration – Low Power Coalition 51 Power DomainPower Mode PD0 PD1 PD2 PD3 PD4 PD5 PM1 1.2V 1.2V 1.2V 0.74V 0.74V 0.74V PM2 1.2V PSO 1.2V 0.74V 0.74V 0.74V PM3 1.2V 1.2V PSO 0.74V 0.74V 0.74V PM4 1.2V 1.2V 1.2V PSO 0.74V 0.74V PM5 1.2V PSO PSO PSO 0.74V PSO Driver PD4:0.74V PD0: 1.2V (Default, Always On) PD5:0.74V PD3:0.74V PD2:1.2V PD1:1.2V PSOcntl PSGcntl ISOcntl Validated CPF and CPF-based flow for major low power methodologies in NEC Electronics 386 checkpoints evaluated successfully CPF describe-ability Multi-Supply-Voltage (MSV) Power Shut Off (PSO) State Retention Logic (SRL) Variable Voltage Library (VVL) Clock Tree Gating (CTG) CPF based flow will be in use from Q3/2007 NEC Proof Point Project Using CPF Based Low Power Solution NEC ElectronicsNEC Electronics CorporationCorporation 65nm 6 Power Domains 5 Power Modes 2 Supply Voltage
- 46. – 50 –InnovationThrough Collaboration – 50 –Innovation Through Collaboration – Low Power Coalition 50 Fujitsu Proof Point Project Using CPF Based Low Power Solution CPU1 CPU2peripherals Power Switch 90nm 940K instances 11 Power Domains 19 Power Modes Power Domains ● Verified with test design PSO functional verification with simulation Low power structural and physical check (Shifters/Isolators/Power switches) Domain aware place and route ● Conclusion Functional verification is necessary for complex PSO design for design bugs Structural check with CPF could verify LP design Fujitsu will support CPF-based ASIC flow for their customers Silicon Proven September ‘07Silicon Proven September ‘07 DVFS
- 47. – 52 –InnovationThrough Collaboration – 52 –Innovation Through Collaboration – Low Power Coalition 52 Power Forward low-power platform SoC results ● CPF-based functional verification (using simulation) catches system level power issues early in the flow ● Use of CPF ensured what implementation built was what was verified • SoC consists of 11 islands • 3 major power consumers -RISC CPU, VLIW DSP & L2 System Cache are controlled using DVFS • High bandwidth expansion ports enable extension, with graphics or cellular modem subsystems NXP Proof Point Project Using CPF Based Low Power Solution
- 48. Low-Power Methodology A PracticalCase Study in Low-Power Methodology • Special thanks to NXP Semiconductors
- 49. Si2 – InnovationThrough Collaboration Low-Power Methodology • New! Educational eBook resource for industry… no-cost download (168pp.) • Contents include: – LP Techniques - Design / Verification / Implementation w/ CPF – Real end-user chip design experiences courtesy, PowerForward.org
- 50. Additional Chapters inthe pipeline • Low power test - Cadence • TSMC –Reference Flow 8.0, 9.0, Low Power Physical IP • ARM (3) – 1176 RM, Cortex A8, historical LP collaboration in SDC, How to use ARM LP IP • UMC – Ulterior PPP (with ARM) • Sequence -- Architectural power exploration • Faraday – Low power service success • GUC - success story • AMD – PPP
- 51. Raising The Low-PowerDebate
- 52. What Is TheLow-Power Coalition? ● Flow-based solutions Standards to promote integration of open technologies into cohesive flows CPF was contributed to LPC 4Q'06, approved as Si2 standard in March 2007 CPF is fully open to the entire industry at no cost – anyone can influence direction Analyze / develop semantic consistency across data exchanges ● User-centric and comprehensive Focused on user needs for faster adoption into production chip design flows Owns the industry's low-power roadmap of requirements Comprehensive: enabling software, training & educational materials, articles, books, conferences, press coverage, etc.
- 53. LPC Member Companies ●Advanced Micro Devices* ● ARM ● Atrenta ● Azuro ● Cadence Design Systems ● Calypto Design Systems ● Chipvision Design Systems AG ● Entasys Design ● Freescale Semiconductor ● IBM Corporation ● Intel Corporation ● LSI ● NXP Semiconductors ● Sequence Design ● Virage Logic • 6 End-Users • 7 EDA Companies • 2 IP Providers (*) = LPC Chair
- 54. LPC Structure, WorkingGroups ● Full LPC membership (AMD, Chair) Business/policy & standards approvals ● Technical Steering Group (TSG): charters working groups, owns the low-power technology roadmap Includes 3 Chief Architects (Cadence, IBM, LSI) ● Active and completed working groups: Flow WG – align on low-power reference design flow and design techniques to drive clarity for enhancements Data Model and API WG – map clear semantics and data relationships in CPF, add API interface support to CPF Format WG – define priorities and detailed requirements (RFT); define the next revision of CPF (v1.1) > 100 pp. of (backward-compatible) enhancements Format Comparison WG – report on technical comparison of CPF and UPF (Done, results widely shared)
- 55. LPC Structure Full LPCMembership Technical Steering Group 3 Chief Architects Flow WG Format WG Format Comparison WG Data Model & API WG
- 56. LPC Working Groups ●Flow Working Group Definition of complete reference flow from ESL to GDSII Target completion date: 2Q08 Analysis of power stimuli for SoC power estimation Target completion date: 2Q08 Compilation of all known low power design techniques Target completion date: 2Q08
- 57. LPC Working Groups ●Data Model Working Group LP Glossary v1.0 completed and posted for download Developing UML-based models to support enhanced power-aware design Will be based on OpenAccess data model Target date: 1H08
- 58. LPC Working Groups ●Format Working Group Develop format extensions requirements document Target date: 1Q08 (DONE) Open RFT, receive contributions DONE CPF 1.1 standardization target: Aug '08 CPF roadmap alignment across both Flow and Data Model WGs
- 59. Recent LPC /CPF Publicity
- 60. Recent LPC /CPF Publicity
- 61. – 1 –InnovationThrough Collaboration – 1 – Innovation Through Collaboration – Low Power Coalition Format Enhancement Requirements Immediate - Requirements for Version 1.1 (extension to 1.0) Hierarchical flow Support. Memory modeling styles and support. Gatelevel verification Flow CPF support. Power estimation Support Clocking and related updates are required to drive power optimization. Medium Term – Requirement for CPF 1.2 Pre-Si and post_Si power modeling and budgeting. Test power definitions not represented in CPF. Investigate Load_foreign. IO modeling and representation. Long term - Next Generation CPF needs to drive debug related to power. CPF based system level definition. 1.1 1.2 2.0
- 62. – 3 –InnovationThrough Collaboration – 3 – Innovation Through Collaboration – Low Power Coalition Hierarchical Flow – Bottom Up Chip Level power Structure CPF Memories Hard IP with (Behavioural) Hard IP with RTL or Gates Soft IP RTL Multiple CPF Multiple CPF Multiple CPF Multiple CPF
- 63. – 64 –InnovationThrough Collaboration – 64 – Innovation Through Collaboration – Low Power Coalition: Si2 Confidential Soft IP Reuse ● IP is defined with multiple power structures and functionalities ● At chip level, part of the power structures or functionality will be used ● Need to Merge power domains Reconfigure power domains Reconfigure power rules Merge rules and resolve precedence Integrate power modes Need to be capable of composing modes description from combination of power supplies and other modes. Allow block level configurations to refine top level power mode.. Should be capable of specifying the performance parameter.
- 64. – 62 –InnovationThrough Collaboration – 62 – Innovation Through Collaboration – Low Power Coalition: Si2 Confidential Hierarchical Flow Requirements ● Perspective Enable IP reuse Reuse Design Hierarchy and better organization. Enable Low power Custom IP Integration and verification. Support Bottom-up and Top Down Flow ● Ensures Consistent Representation Consistent Integration style Consistent Verification Consistent Rules, semantics, precedence policy.
- 65. – 67 –InnovationThrough Collaboration – 67 – Innovation Through Collaboration – Low Power Coalition: Si2 Confidential Custom IP Support Requirements ● A Hard IP can be connected to multiple power ports and significant logic may belong to multiple domains. Assigning the entire component to single domain may create incorrect representation. ● Support integration of custom IP. To most of the flow it is considered a blackbox ● Support Verification of Custom IP using CPF IP may have non-trivial power structures IP has a behavioral model with no relation to hierarchy of power domains. ● Need to Maintain IP level power control sequence. Define the power structure using only boundary ports and registers. Provide hooks to use the behavioral model Integrate power connections at chip level
- 66. – 74 –InnovationThrough Collaboration – 74 – Innovation Through Collaboration – Low Power Coalition: Si2 Confidential Power Network Component Models ● Power Network Component Switches Regulators Converters ● Provide an approach to model the power network components. Component input Component output Component Efficiency Component Electrical Characteristics ● Need recommendations from flow group and other working groups.
- 67. – 77 –InnovationThrough Collaboration – 77 – Innovation Through Collaboration – Low Power Coalition: Si2 Confidential Proposed CPF Roadmap 2.0 1.2 1.1 Start H1/09Start Q1/08 Start H2/08
- 68. Si2 – InnovationThrough Collaboration Summary of Low-Power Collateral 1. CPF v1.0 Standard 2. CPF v1.0 Parser software 3. CPF Pocket Reference Guide 4. CPF On-line Tutorial - both in English and Mandarin (2.5 hrs) 5. Low-Power Glossary of Terms 6. CPF v1.1 Requirements Document (and RFT) 7. Low-Power Industry Roadmap 8. “A Practical Guide to Low Power Design” (168pp. ebook) For downloads, go to: www.si2.org/?page=726
- 69. Silicon Integration Initiative1 DFMC New... CPF Relational Analyzer
- 70. Silicon Integration Initiative2 Why • Structured, Low Power design methodology is currently the exclusive and elite domain of a few “Power Users” The CPF Relational Analyzer is for everybody else • Simple, Interactive Training Tool • Realizes in open source software the key concepts of the CPF Format • Accelerates the CPF learning curve LP Design Using CPF - Who me?
- 71. Silicon Integration Initiative4 Plenty of Room for Confusion (and Errors) Multiple Source Files Multiple GroupsTop Level Power Targets Power Domains Multiple Levels of hierarchy Same Domain Constraints Level Shift Rules Multiple Libraries w/ Multiple Variants Power Unit mW Power Unit uW Incremental Changes
- 72. Silicon Integration Initiative6 set_design top # Set up logic structure for all power domains set_time_unit us set_power_unit uW create_power_domain -name PDcore -default create_power_domain -name PDalu -instances {inst_A inst_B} -shutoff_condition {!pm_inst.pse_enable[0]} create_power_domain -name PDrf -instances inst_C -shutoff_condition {!pm_inst.pse_enable[1]} create_power_domain -name PD4 -instances inst_D -shutoff_condition {!pm_inst.pse_enable[2]} # Define static behavior of all power domains and specify timing constraints create_nominal_condition -name high -voltage 1.2 create_nominal_condition -name medium -voltage 1.1 create_nominal_condition -name low -voltage 1.0 create_power_mode -name PMhot -domain_conditions {PDcore@high PDalu@medium PDrf@high PD4@low} -default create_power_mode -name PMcool -domain_conditions {PDcore@high PDrf@high PD4@low} create_power_mode -name PMsleep -domain_conditions {PDcore@high PD4@low} create_power_mode -name PMhibernate -domain_conditions {PDcore@low} # Set up required isolation and state retention rules for all domains create_state_retention_rule -name sr1 -domain PDalu -restore_edge {!pm_inst.pge_enable[0]} create_state_retention_rule -name sr2 -domain PDrf -restore_edge {!pm_inst.pge_enable[1]} create_state_retention_rule -name sr3 -domain PD4 -restore_edge {!pm_inst.pge_enable[2]} create_isolation_rule -name ir1 -from PDalu -isolation_condition {pm_inst.ice_enable[0]} -isolation_output high create_isolation_rule -name ir2 -from PDrf -isolation_condition {pm_inst.ice_enable[1]} -isolation_output high create_isolation_rule -name ir3 -from PD4 -isolation_condition {pm_inst.ice_enable[2]} -isolation_output low create_level_shifter_rule -name lsr1 -to {PDcore PDrf} end_design CPF Format Concepts Define PDs Define Nominals PMs Bind PD & NC Rulesand morerules What if this command was in a different file and the IP in PDcore had not been characterized at the “low” nominal condition?
- 73. Silicon Integration Initiative7 CPF Relational Analyzer • Each object in the CPF hierarchy is tracked separately via metadata • Architecture handles hierarchy merging, module cloning & port mapping • Broad analysis – Analyze all objects and all O2O relationships • Deep analysis – Every attribute, every object with every update Interactive and Incremental: Designed for “Hands-on” learners with English as a Second Language Exposes the final state of the design intent compiled from many sources Search and Report capabilities: All searches can use standard wildcards of *, ?, [a-z], [0-9] Any combination of CPF Objects, Property Names and Property Values
- 74. Silicon Integration Initiative5 CPF Information Model
- 75. Si2 – InnovationThrough Collaboration
- 76. Si2 - InnovationThrough Collaboration Thank You!