Low power VLSI design has become important due to increasing integration leading to higher power consumption. Low power design is essential for handheld devices to allow long battery life and better performance. There are various techniques for low power design including reducing supply voltage, minimizing capacitance and switching activity, and employing strategies like clock gating and power gating. Low power design can be achieved at different levels from system to logic to physical design.

2. • Abstract
• INTRODUCTION
• Importance Of Low Power Design
• Sources of Power Dissipation
• Basic principle of low power Design
• Low Power Design Space
• Supply voltage reduction
• Physical Capacitance
• Switching Activity
• Low Power Strategies
• Low power techniques ,CAD Methodologies and Techniques ,Power Minimization
Techniques
• Advantages and Disadvantages
• Conclusion

3. The recent trends in the developments and advancements in the area of
low power VLSI Design are surveyed in this paper. Though Low Power
is a well established domain, it has undergone lot of developments from
transistor sizing, process shrinkage, voltage scaling, clock gating, etc.,
to adiabatic logic. This paper aims to elaborate on the recent trends in
the low power design.

4.  Due to integration of components increased the power comes in lime
light
 It is much important that handheld devices must possess low power
devices
 For better performance
 For long run time (Battery time)

5. • Power is considered as the most important constraint in
embedded systems
• Low power design is essential in:
High-performance systems (reason: excessive power
dissipation reduces reliability and increases the cost imposed
by cooling systems and packaging)
portable systems (reason: battery technology cannot keep the
pace with large demands for devices with light batteries and
long time between recharges)

6. The power dissipation in circuit can be classified into three
categories as described below.
 Dynamic power consumption
 Short-circuit current
 Leakage current

7. Dynamic power consumption: Due to logic transitions causing
logic gates to charge/discharge load capacitance.

Short-circuit current: In a CMOS logic P-branch and N-branch are
momentarily shorted as logic gate changes state resulting in short
circuit power dissipation.
Leakage current: This is the power dissipation that occurs when the
system is in standby mode or not powered. There are many sources
of leakage current in MOSFET. Diode leakages around transistors
and n-wells, Sub threshold Leakage, Gate Leakage, Tunnel
Currents etc. Increasing 20 times for each new fabrication
technology. Went from insignificant to a dominating factor.

9. • Using the lowest possible supply voltage
• Using the smallest geometry, highest frequency devices but operating
them at the lowest possible frequency.
• Using parallelism and pipelining to lower required frequency of operation.
• Power management by disconnecting the power source when the system
is idle.
• Desigining systems to have lowest requirements on subsystem
performance for the given user level functionality.

10.  Three parts that we can perform low power techniques
to reduce power dissipation
 Voltage
 Physical Capacitance
 Switching activity

11.  Voltage reduction offers an effective means of power reduction
 A factor of two reduction in supply voltage yields a factor of four
decreases in power consumption
 But the performance is also getting reduced
 To avoid the above stated problem,
 Threshold voltage should be scaled down

12.  Dynamic power consumption depends linearly on the physical
capacitance being switched
 So minimizing capacitance offers another technique to for
minimizing power consumption
 The capacitor can be kept as small by..
 Minimum logic
 Smaller devices
 Fewer and shorter wires

13.  There are two components to switching activity :
 which determines the average periodicity of data arrivals
 E (sw) which determines how many transitions each arrival will generate
 Switching activity is reduced by
 Selecting proper algorithms architecture optimization,
 Proper choice of logic topology
 Logic level optimization which results in less power

14.  Input Pattern Dependence
 Logic Function
 Logic Style
 Circuit Structure

17.  Clock Gating
 To reducing dynamic power dissipation
 works by taking the enable conditions attached to registers, and uses them to
gate the clocks
 Power Gating
 High Vt sleep transistors which cut off VDD from a circuit block when the block
is not switching
 Also known as MTCMOS - Multi-Threshold CMOS

18.  Low power VLSI design can be achieved at various levels of the design process
 System Design
 inactive hardware modules may be automatically turned off to save power
 Behavioral Synthesis
 The behavioral synthesis process consists of three steps:
 Allocation
 Assignment and scheduling
 These steps determine how many instances of each resource are needed
 Logic Synthesis
 Physical Design

19.  Reducing chip and package capacitance
 Process development such as SOI with partially or fully depleted wells
 Advanced interconnect substrates such as Multi-Chip Modules (MCM).
 Scaling the supply voltage
 Very effective
 But often requires process technologies
 Employing better design techniques
 The investment to reduce power by design is relatively small
 Using power management strategies
 Various static and dynamic power management techniques

23.  Low power VLSI is needed
 Increasing of handheld devices
 Increasing of complex device structure
 Long battery life
 Long device life